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Since 1984, nearly $45M has been invested in developing innovative methodologies to decrease life-cycle risks for the next generation of electronic products and systems, and to provide an educational and technological infrastructure for their rapid dissemination and use. We now offer an extensive set of resources to help engineers assess, mitigate, and manage risks in electronic products. These include web-based documents and tools to: conduct parts selection and management; conduct cost-effective accelerated testing and screening; predict reliability based on physics of failure and using virtual qualification software; design using components outside their rated temperature; design and utilize high temperature electronics; and model life cycle economics. CalcePWA and CADMP II reliability assessment software was developed at CALCE EPSC over the past 15 years. It is the most advanced reliability assessment and virtual qualification tool currently available, providing engineers with a silicon-to-systems accelerated product qualification capabilities. To access more information on the CALCE software products, click here. The center offers a wide access to a collection of web-based documents, called webbooks, that cover areas of critical importance in electronic products and systems development, ranging from solder-joint fatigue analysis and accelerated test development to cost analysis and supply chain management. To access a complete list of CALCE webbooks and their short descriptions, click here. Webbooks of particular interest to the computer and consumer electronics industries are listed below: The CALCE CCA Failure Mechanism Handbook is an evolving technology that is intended to allow design engineers, product managers, reliability analysts, and failure analysts to rapidly evaluate failure risks for circuit card assemblies (CCA). This resource describes, compares, and critiques different failure models for CCAs. Examples include thermomechanical fatigue, vibration fatigue, mechanical shock/warpage damage, and chemical/corrosion damage. Access to online failure calculators is also provided. The component knowledge base webbook was developed to provide engineers with valuable background information on a variety of components including analog ICs, connectors, memory, potentiometers, cables, electromotors, MEMS, resistors, capacitors, magnetics, PCBs and thermistors which are used in electronic products. This webbook is intended to aid engineers in: (1) identifying critical components in a product based on system application requirement and component technologies, (2) understanding design and manufacturing (construction, material, reliability, quality issues) of these components, (3) analyzing risks related to the application of these components, (4) evaluating identified risks using analytic and reliability test methodologies, (5) developing component reliability and quality specifications, (6) developing guidelines for proper application of the components in system design, manufacturing, and test, (7) identifying root-cause of failures related to the components, and (8) investigating component quality/reliability function enhancement and cost reduction opportunities. The "Asian Update" is a service which provides information on the Asian electronics industry. It consists of webbooks and articles covering past, current and future developments, the economic and industrial impact, and research in the Asian electronics industry. The purpose is to provide engineers and managers with information on the technologies, manufacturing procedures, and capabilities of Asian countries. This webbook contains information on approaches to computational modeling, current capabilities of commercial EMC/EMI software, and the fundamental mathematical principles behind EMC/EMI modeling and analysis. It also contains various EMC/EMI example problems. A limiting requirement for some parts is escape routing. If a part's I/O are in an area array format (as opposed to peripherally bonded), the part can not be wired into the system until all of its I/O are routed out from under the part. This situation is encountered for flip chip bonded die and die in various array format chip scale packages such as BGAs (Ball Grid Arrays). The process of liberating I/O from an array is called escape routing. If the array is small enough (small I/O count), or the line width and line spacing in the board is fine enough, it may be possible to escape all the I/O on the top layer of the board. More often, however, some I/O must use vias to drop to other layers to be escape routed. If additional layers must be used, the combination of the part I/O pitch and connection size, and the via and/or hole capture pad sizes must allow the placement of a via or hole capture on the board within the part I/O array, or it is impossible to drop unescaped I/O to deeper layers. In addition, many board technologies, especially microvia Printed Wiring Boards (PWBs), have practical limitations on the number of layers that can be fabricated. A part that requires too many layers to escape route may have to be rejected. This tool can be used to: 1) Determine whether a specific part can be escape routed when interconnected to a specific board technology, and 2) Determine the footprint occupied by the part on the top layer of the board. This resource provides an introduction to Integral Passives (IPs). The resource covers materials, economics, and failure issues related to using IPs. This model provides an application-specific economic analysis of the conversion of discrete passive components (resistors and capacitors) to integral passives that are embedded within a printed circuit board. The model performs three basic analyses: 1) Board size analysis is used to determine board sizes, layer counts, and the number of boards that can be fabricated on a panel; 2) Panel fabrication cost modeling including a cost of ownership model is used to determine the impact of throughput changes associated with fabricating integral passive panels; and 3) Assembly modeling is used to determine the cost of assembling all discrete components, and their associated inspection and rework. Display technology is changing at an ever increasing pace. New developments focused towards optimizing power, size, weight, performance and cost are revolutionizing the display industry. The flat panel display market is projected to be around $30 billion worldwide in 2003, of which 86% is expected to be liquid crystal displays. Furthermore active matrix LCD are projected to be the dominant LCD technology in the coming years. Apart from consumer electronics, increasing use of LCDs in critical applications like defense, avionics and automobiles has evoked the need to understand the reliability of LCD devices. This web handbook is part of this effort to bring together all the scattered data on LCD reliability at one place for the benefit of CALCE consortium members. The Microelectronic Defects Database (MDD) is a guide to understanding defects and their impact on microelectronics reliability. It allows the user to analyze a failure, to find the root cause defects, or to examine a defect and determine what failures it can cause. To facilitate defect identification and failure analysis, detailed diagrams and high magnification pictures taken with a wide variety of analysis techniques are provided. The philosophy behind this webbook is rooted in the physics-of-failure approach to microelectronics reliability assessment. This webbook can be used to answer the following questions: What defects, environmental, and test or screen loads are the reliability drivers for the device? What magnitudes of defects should be allowed to pass the screens? and, What is the correlation between the defect magnitudes and the operational life? From calculators to the control panel on the space shuttle, printed wiring assemblies (PWA's) are prominent in today's technological world. Where are they made? How are they made? How are they tested? The answers to these questions and more are in this webbook. Discover the manufacturing and assembly process of PWB's and companies that make this process work. The purpose of failure analysis is to determine the root-cause of what, why, how, and where products can fail. Expert systems, which use decision trees and material data to create solutions to complex problems, can provide users with improved problem-solving capabilities without the expense of additional employees or facilities. This expert system for failure analysis, developed by the CALCE Research Center, provides designers, manufacturers, and users of electronic products a powerful tool in identification and corrective/preventive actions. At this time, our expert system is set up only for failures at the printed wiring board, but will soon include all possible failure mechanisms and defects that can occur in electronic products and systems. Over time, soldering technology has developed from an art into a high-technology science - an evolution chiefly influenced by the pressure placed on the soldering industry by advances in microelectronics. This book addresses the major facets of modern soldering technology and the science behind that technology. |
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