A two-phase parts selection and management benchmarking activity has just been completed with Nortel, Phase one was conducted with respect to Nortel's manufacturer quality and part quality and integrity assessment. Margaret Jackson at CALCE EPSC spent three days with Nortel's component engineers in August 1998 conducting interviews and gaining understanding of Nortel's processes. A report was generated on the findings, and process improvement recommendations were offered to Nortel. The results of the visit were used to enhance the Consortium's work with respect to manufacturer quality, part quality and integrity assessment.
Part two of the benchmarking activity was conducted with respect to Nortel's environmental mismatch assessment and mitigation: performance, reliability and assembly processes. In December 1998, Dr. Peter Sandborn, also from CALCE EPSC and Ms. Jackson spent three days with Nortel engineers involved in the aforementioned processes, again conducting interviews and recording observations. The results of the December study will also be used to offer Nortel process improvement recommendations, and to enhance the Consortium's guidebook contents.
In addition to input from Nortel, the Consortium continues to receive feedback from its members, including Aerospatiale, AlliedSignal, British Aerospace, Honeywell, Lucas Aerospace, and Smith Industries on the contents of the Consortium's draft document. For further information, contact CALCE EPSC at (301) 405-5323.
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In 1995-1997, CALCE developed a comprehensive physics-of-failure approach for maximizing test-time compression by simultaneously applying different environmental loadings. This approach was demonstrated on electronic circuit card assemblies (CCAs) using combined vibration and thermal cycling. CALCE also created a web-based facility to interactively help users implement this PoF approach through the use of detailed flowcharts, worksheets, models, databases and on-line analysis tools. In the current project, CALCE will demonstrate this PoF approach on production hardware assemblies, in collaboration with two CALCE sponsors.
One of the electronic assemblies is for a portable computer used in a ground mobile military environment and consists of a CPU motherboard with an attached mezzanine board. The other assembly, from an automotive company, controls various passenger compartment functions. Both assemblies are densely populated with a variety of through-hole and surface mount components. Reliability of the two assemblies for their field use conditions will be estimated from the accelerated qualification tests. The use of calcePWA software, on-line damage assessments tools, and web-based accelerated qualification guidelines will be actively used in this study. For information, contact Dr. A. Dasgupta at (301) 405-5251 or dasgupta@calce.umd.edu.
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CALCE has teamed with Dense-Pac Microsystems, Inc., a volume manufacturer of proprietary three-dimensional (3D) high-density memory and system packaging to form an alliance to further the advancement of 3D electronics. The new alliance builds on the experience and the structure of the CALCE-EPSC, which includes more than 40 member companies. The alliance includes companies and organizations that are suppliers and users of 3D electronics packaging, as well as developers of design tools used to support 3D electronics packaging techniques.
CALCE EPSC 3D was formed to develop a scientific basis for innovative 3D electronics packaging, and establish an educational and technology transfer infrastructure for the rapid dissemination and utilization of any new developments created as a result of its efforts. The alliance will create technology roadmaps for unique memory systems and sponsor technical sessions at major electronics conferences. The alliance will establish a web site devoted to the enhancement of 3D electronics packaging and to educate users and designers of their functionality. The first alliance meeting was held January 21, 1999, at CALCE and included participation from Matra, NASA, Alcatel, Irvine Sensors, Johns Hopkins, Dense-Pac Microsystems, Cray Research, GE Research Center, Teledyne, Army Research Center, NCMS and others.
According to Dense-Pac's Chief Executive Officer Richard Dadamo, in forming this consortium of major corporations, we have, in conjunction with the University of Maryland, taken a forefront position in 3D electronics packaging manufacturing. We are committed to expanding the uses of and the potential markets for our technology and manufacturing processes. Our participation as the joint leader in the consortium will enable us to better assess the future trends in memory technology and to meet the needs of the market.
For further information, contact Dr. Peter Sandborn at (301) 405-3167 or sandborn@calce.umd.edu.
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CALCE EPSC has been awarded a two year contract from NASA Jet Propulsion Laboratory to evaluate the manufacturing processes associated with fabricating advanced high-frequency modules composed of a combination of micromachined (MEMS) and electronic solid state components (Si/Ge HBTs). Evaluation of the manufacturing processes includes identification of the process steps, evaluating compatibility of the necessary processing, cost analysis, and yield analysis. MEMS structures that will be evaluated include: compliant and high-isolation switches, Radio Frequency (RF) filters and transmission lines. The process compatibility of these structures with Hetrojunction Bipolar Transistors (HBTs) will focus on process temperature, etching, and planarity issues.
For further information on this project please contact Dr. Peter Sandborn at at (301) 405-3167 or sandborn@calce.umd.edu.
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A program entitled "Life Cycle Cost Reduction Through a Cradle-to-Grave Physics of Failure Approach to Sustanable Electronic Systems," has been selected for award by the Air Force ManTech program at Wright-Patterson Air Force Base under BAA 98-16. The 51 month program was developed by a team composed of CALCE, AlliedSignal, Price Systems, and the F-16 System Program Office. Working together, the team will dramatically decrease life cycle costs by managing life cycle risks associated with the design and manufacturing of sustainable military electronic systems. The approach taken in this program is not making old technology parts available longer, or making the maintenance of systems less expensive, but rather, to focus on designing and manufacturing systems for the defense industry that have lower life cycle sustainment costs, by instituing a cradle-to-grave Physics of Failure based program as an up-front (pro-active) approach to achieving system reliability, manufacturability, technology risk management, and affordability. Methodologies addressed within this program include:
- Virtual qualification and technology risk assessment
- Application-specific simulation and structured testing
- Health monitoring
- Supplier risk assessment and intervention
- Environmental envelope mismatch management
- Technology life cycle mismatch (obsolescence) management
- Maintenance (line disposable units as alternatives to line replaceable units)
In addition to developing and implementing the above methodologies, this program will identify new metrics to better assess risk and use them to characterize economic impact models for the new methodologies. The economic models will be integrated with other contributions to the life cycle, to form a complete life cycle cost analysis. Implementation of the life cycle cost modeling will leverage commercial software tools from Price Systems. Use of this existing software greatly reduces the required effort and risk in successfully delivering a userful economic analysis solution to integrate with PoF in this program. To facilitate a high-impact prototype implementation, this program will leverage AlliedSignal's Adaptive Military APU Control (AMAC) program. The AMAC program has aggressive goals including a significant reduction in development cycle time for follow on applications, increased reliability and reduced recurring and non-recurring costs. Associated with the AMAC program, AlliedSignal will perform a prototype implementation on electronic controls for Auxiliary Power Units used in F-16, F-18 and Army helicopters. This implementation will be used to measure the effectiveness of the methodologies and their implementation in the design and manufacturing process.
For further information on this program, contact Dr. Peter
Sandborn at (301) 405-3167 or sandborn@calce.umd.edu.
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One of the key challenges facing the design of future electronic systems is the growing size of thermal management hardware in the face of shrinking system sizes. Taking computing products as an example, the thickness of portable computers has been reduced from around 40 mm in 1993 to less than 20 mm today, while the heat dissipation from the microprocessor chip has increased from around 2 W to 15 W in some designs. Trends indicate that advanced workstation computers will be built with an increasing number of chips in ever tighter three-dimensional space. The heat fluxes at the chip level for high performance systems are projected to exceed 25 W/cm2 in digital electronics by 2012. For cost/performance systems, heat fluxes are projected to increase from about 10 W/cm2 to 15 W/cm2. For certain classes of systems, such as communications network devices, power electronics, and laser diodes, the projected chip level heat fluxes for the next decade are well over 100 W/cm2.
Current state-of-the-art for infrastructure equipment involves increasingly larger air cooled heat sinks. Enormous pumping power will be needed if one resorts to forced convection air cooling for large systems of the future. While demonstrations of large thermal dissipation capabilities through various advanced cooling schemes have been made over the past decade, air cooling has remained the mainstay in most electronic systems. It is clear that for a number of applications, direct air cooling will have to be replaced with other high performance compact cooling techniques.
In order to address the above challenges, CALCE EPSC has been awarded a three-year $300,000 contract from the Semiconductor Research Corporation (SRC) for the development and implementation of entirely passive, two phase compact thermosyphons using microfabrication concepts. Thermosyphons are fluid filled dlosed loop devices, incorporating an interconnected evaporator and condenser. The working fluid undergoes a liquid to vapor phase transition in the evaporator, thereby absorbing the latent heat of vaporization. The vapor then travels to the condenser, where the heat is lost to the ambient and the working fluid condenses to liquid. By using microfabricated boiling enhancement structures the evaporator can be made very compact. Baseline demonstrations of these devices have been recently made, where cooling capabilities of over 80 W/cm2 have been achieved. The new effort will be directed towards significant improvement of the performance of these devices through experimentation and modeling. Technology demonstration will be achieved by prototype implementation on enclosure sizes of relevance to portable electronic applications. A parallel thrust will be to establish the reliability and cost effective manufacturing methodology for these devices.
For further information on this study please contact CALCE EPSC at (301) 405-5323.
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The IEEE Working Group, chaired by Dr. Michael Pecht, is pleased to announce the approval of the IEEE P1413 Draft Standard Methodology for Reliability Prediction and Assessment for Electronic Systems and Equipment. With input from hundreds of experts in the electronics industry during draft standard development, the working group received notice of IEEE 1413 approval on December 8, 1998. The standard is now undergoing editing by the IEEE, and will be publicly available in Spring 1999.
IEEE 1413 establishes the framework around which a reliability prediction methodology must be structured. The criteria identified in IEEE 1413 must therefore be met by reliability predictions said to meet IEEE requirements. The IEEE Reliability Prediction Working Group is continuing its efforts in reliability prediction through the development of a guide document, designed to accompany IEEE 1413. The Working Group will identify available reliability prediction methodologies, and will evaluate those methodologies against the criteria presented in IEEE 1413.
The IEEE Working Group will use a matrix for the evaluation of various reliability prediction methods against the IEEE 1413 criteria. The results will be compiled into a guide document, designed to accompany IEEE 1413. This guide document will enable users to make an informed decision regarding the selection of a reliability prediction methodology.
The guide document development efforts began in September 1998 when the IEEE Reliability Prediction Working Group identified the need to addresss teh currently available reliability prediction standard with respect to their ability to meet the identified criteria. For information, contact Dr. Michael Pecht at (301) 405-5323.
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IEEE P1332 was officially approved on June 30, 1998. It provides guidance to suppliers to plan a program that suits their design philosophy, the product concept, and the resources at their disposal, so that every activity adds value. The next step with respect to IEEE Reliability Program efforts is to develop a guidance document for P1332, which will include specific reliability assessment procedures. The Dallas, Texas chaper of the IEEE has agreed to begin preliminary research into this development. The group plans to complete the standard in the Fall of 1999, and anticipates that the IEEE 1413 accompanying guide will be publicly available by the Spring of 2000.
Anyone interested in obtaining information about guidebook development is encouraged to contact CALCE EPSC at (301) 405-5323.
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Solder joint problems have traditionally plagued the electronic industry as new package syles are introduced into new or existing designs. The drive to reduce product size with the introduction of BGAs, CSPs, and fine pitch surface mount package styles has raised both manufacture and reliablity concerns. Praticing design engineers rarely have the time and the luxury to model and run a complex non-linear finite element analysis to see whether or not they will have a problem with a new package style or design. Unfortunately many designers take the conservative approach and use package styles they have used before, just because they don't have rapid analysis capabilities. But watch out! This approach may not work in the future since some new components are only being offered in the new package styles.
CALCE EPSC has recognized this problem and has moved their solder joint failure models onto the web for more open access. Practicing engineers can now directly access and run the most recent CALCE solder joint failure analysis models directly on the web. These models are available in a stand alone form and are located on the CALCE website in the Software Products section.
The solder joint models are available in various levels of sophistication, ranging from the low order models that are designed for rapid assessment and quick "what-if" calculations to the increasingly complex models that take longer to run but provide more detailed capabilities to capture geometric variabilities. The models are run from simple input forms for various common package styles. The models also easily analyze complex loading profiles composed of a combination of thermal profiles. Several statistical utilities are also available for the calculation of various times to failure for different assumed failure distributions. For information contact Dr. Michael Osterman at osterman@calce.umd.edu.
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