| Created: 5/21/95 | Updated: 11/15/96 |
Developments in the design and manufacture of electronic components indicate that the currently accepted temperature limits of -55°C to 125°C may be unduly restrictive. Many systems should be able to perform adequately up to 200°C with no changes. In other cases, system failures could be avoided by selecting different materials or varying design parameters to accommodate higher steady-state temperature use. For example, conductive filament formation in FR-4 boards can be minimized at high temperatures by choosing either a wider conductor spacing, a lower operating voltage, or a more moisture-resistant laminate system.
The CALCE EPRC is conducting a two-phase study to identify the technical challenges involved in operating systems at elevated temperatures. The first phase focusses on collecting and analyzing material data for temperatures up to 200°C, including mechanical, electrical, and thermal properties, and their relationship to temperature within that range, are being assessed. The most important properties for system operation and reliability are being emphasized. At the completion of the first phase, a report on the temperature dependencies of material properties for each packaging element will be available to CALCE EPRC members.
The knowledge gained in the first phase will be used in the second phase to evaluate six candidate electronic hardware designs for a wide range of modules, each of which contains multiple components, cards, and associated hardware. Each system will be evaluated on the basis of its parts list, which includes information on the device technologies, the package family types, the assembly and interconnect materials, and the board constructions. In addition, actual units and assembly drawings will be used to determine the locations of the parts in the system. The materials-related concerns that arise in these systems at high operating temperatures will be identified, together with strategies for accommodating elevated temperature use through materials selection and design variation. For more information, please contact Dr. Patrick McCluskey.
The temperature ramp rate used during reflow is a critical process parameter affecting the occurrence of delamination and cracking. The magnitude of the stresses generated in the PEM due to mismatches of the coefficients of thermal expansion (CTE) at the interfaces and the presence of moisture will be lower if lower temperature ramp rates are used. The lower ramp rates also facilitate the efficient desorption of moisture from the devices during the preheat phase of the reflow process.
Experiments are being conducted at the CALCE EPRC to investigate these effects. An experimental setup has been established that can be used to heat PEMs through any desired temperature profile, while simultaneously observing their X-ray images. Acoustic microscopy, followed by environmental scanning electron microscopy (see article on Electronic Packaging E-SEM Applications), are then used to quantify the delaminations and cracks. Preliminary results have indicated that popcorning can be controlled by using suitably low temperature ramp rates (see graph below).
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Infrared reflow temperature profiles indicating ramp rates and
amount of PEM cracking.
Initial tests were conducted on 84-lead plastic quad flat packs (PQFPs) subjected to 168 hours of 85°C/85%RH (IPC Level I). The devices had a moisture content of approximately 0.25% (by weight). They were heated through the reflow cycle, making use of a range of temperature profiles, in order to isolate the ramp rate value at which cracking just begins to occur. The devices remained intact when ramp rates of 0.25 and 0.5°C/second were used. A small crack was detected when 0.75°C/second was used, and full-blown cracking was observed when 2.0 and 5.0°C/second were tested. In this case, the ramp rate necessary to avoid popcorning was low, an understandable because the devices had an extremely high moisture content. Tests were also carried out after subjecting the devices to 30°C/60%RH for 168 hours (IPC Level III) and 72 hours (IPC Level IV). The moisture content of these devices was very low, and popcorning was not detected even at high ramp rates.
The use of lower temperature ramp rates permits the safe presence of greater amounts of ingressed moisture, resulting in the need for fewer precautions during handling or storage. Lower throughputs due to slower ramp rates would be compensated for by a corresponding decrease in the time and money spent on baking and drybagging. For more information, contact Dr. Michael Pecht at (301) 405-5323.
The CALCE EPRC recently hosted an advanced technology workshop to discuss the CFF failure problem and those experiments and models that could be used in design and qualification of woven laminates used in PWBs and MCM-L. Twenty-five people attended the workshop, representing sixteen organizations, including users and vendors of PWBs and MCM-L, laminate vendors, glass fiber vendors, and silane coupler vendors. Presentations covered the role of PWB/MCM-L materials selection (laminates, glass fibers, and coupling agents), board design, manufacturing, and the environmental factors that cause field failures, including moisture absorption, contamination, and temperature.
The workshop resulted in the development of an experimental program for CFF testing and evaluation. The focus of the experiments will be on low-voltage and fine-line PWB and MCM-L applications. Five materials (FR-4, HT- FR-4, BT, CE, polyimide) will be tested. The objective is to develop models for use in design and qualification of woven laminates used in PWBs and MCM-L. For additional information, please contact Dr. Michael Pecht at (301) 405-5323.
Figure 1: Transimpedance amplifiers: Surface defects due to reactions between the polymide film and metallization.
Figure 2: High-density interconnects: The third arrow points to an area of polymide/metallization debonding and the first, second, and fourth arrows point to areas of polymide/polymide delamination.
Figure 3: Printed wiring boards: Fiber/resin debonding along the glass-fiber bundleedge near a plated-through-hole.
Use of non-woven-fiber PCBs may eliminate certain board failures, such as electrical shorts caused by conductive filament formation (CFF). CFF-induced failure has been a problem industry-wide due to copper ion migration along the interfaces between reinforcing fibers, such as glass, and matrix materials, such as epoxy resin. When the fibers in non-woven-fiber laminates are shorter than the distances between the two conductors, electrical shorts caused by CFF may be eliminated in the dielectrics. The picture below shows a cross-sectional area near a plated-through-hole (PTH) in a non-woven-fiber PCB. The chopped fibers are randomly distributed without trace of connections between PTHs.
Microstructural analysis, mechanical tests, thermal mechanical tests, and environmental tests are currently being conducted to characterize the non-woven-fiber boards. Characterizing this type of PCB will allow designers and manufacturers to understand the effects of design changes and process variations. For more information, please contact Dr. Michael Pecht at (301) 405-5323.
Cross-section of non-woven-fiber printed circuit board near a plated-through hole.
Simulations use the computational fluid dynamics (CFD) approach to determine air flow patterns within the enclosure and the temperature responses within the air, circuit board(s) and electronic packages. The effects on temperature of various parameters, such as vent size and placement, substrate, and package characteristics are being evaluated. These results will be validated with a series of measurements. Sample results of three-dimensional computational modeling for a single package mounted on a substrate within a vented box are presented below as temperature and velocity vector distributions for two vent configurations. The pronounced effect of vent location is quite apparent. For further information on this study, please contact CALCE EPSC.
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Velocity vector (left) and temperature (right) distributions for
two different vent configurations.
