Uncooled infrared focal planar array model.
| Created: 5/21/95 | Updated: 11/15/96 |
The Texas Instruments Uncooled Focal Planar Array (UFPA) is a new infrared detector that utilizes the electric properties of Barium Strontium Titanate (BST), operated under constant bias, to detect infrared radiation; it does not require cryogenic cooling . The infrared radiation absorbed by an optical coating in intimate thermal contact with the BST element induces a temperature change causing a variation in the polarization and capacitance of the material. This is sensed as a volatge fluctuation. To form an image, a planar array of BST elements (or pixels) is used to collect incident radiation over a given area; the base of the array is kept constant at 23 degrees Celsius using a thermo-electric cooler. Resolution of the infrared image is dependent on th e temperature gradient through the structure. The thermal effect of the incident infrared rays on the surface of the array determines performance and its subsequent effect on the reliability of the assembly.
The CALCE EPRC has used the physics-of-failure approach and finite element modeling to develop software tools to assess UFPA reliability. The software uses a coupled global-local finite element method to assess the thermal and thermo-mechanical response. Modifying dimensional and material parameters allow alternative designs to be evaluated. For more information, please contact Dr. Don Barker at (301) 405-5264.
Uncooled infrared focal planar array model.
The project targets the rules for circuit design, schematic capture, and part list generation. So far, design rules have been captured from the following groups:
To refine and standardize the methods used for characterizing the behavior of packaging and interconnect materials and structures currently used by the U.S. microelectronics industry, the CALCE EPRC has entered into a Cooperative Research and Development Agreement (CRADA) with NIST, IBM, Delco, Digital Equipment, Texas Instruments, Motorola, DuPont, Dow, NASA-JPL, DoE-Sandia, and Navy-Crane. The objective is to create a forum on advanced microelectronic packaging and interconnect material meteorology.
The forum will consider technical advancements needed in materials measurements and standards to support the data quality and availability requirements of U.S. microelectronic packaging and interconnect designers, manufacturers, and reliability assessors of high volume commercial products. Measurement parameters include electrical, thermal, mechanical, physical, interfacial, and chemical properties and the meteorology for determining time to failure. For more information, contact Dr. Michael Pecht at (301 ) 405-5323.
As part of this study, the CALCE EPRC recently conducted accelerated temperature cycle tests on leadless surface-mount components. Components of various sizes were mounted on printed wiring boards (PWBs) with various coefficients of thermal expansion (CTE ). Leadless solder joints typically fail due to fatigue under temperature cycling; the driving stress is the thermal expansion mismatch between the component and the PWB. The effect of components size and PWB CTE on solder joint stresses is theoretically estimated from a physics-of-failure model for low-cycle solder joint fatigue [IPC-SM785]. Thus, tests at a single temperature history effectively provide a large database for obtaining acceleration transforms.
The acceleration transform curve for a 68 pin leadless chip carrier (LCC), assuming a Weibull distribution at 5% probability of failure, is presented in the figure below. The discrepancies between the experimental data and the theoretical acceleration tra nsform (predicted by the IPC model) are symptomatic of the limitations of the current IPC model for accelerated testing, especially at temperatures below 20 degress Celsius.
Future work will employ a more detailed physics-of-failure model (the CALCE EPRC energy partitioning model) to quantify the experimental results. For more information, contact Dr. Abhijit Dasgupta at (301) 405-5251.
Acceleration transform for 68 pin LCC.
Graphics screen from physics-of-failure based stress margin software.
To validate the application of CFD simulation for complex electronic systems, the CALCE EPRC and Loral Federal Systems Division (Manassas, VA) are comparing simulation results with experimental test data. The electronic system being analyzed is a chassis of commercial VME boards using forced convection air cooling. FLOTHERM, a finite volume-based CFD software package specifically for analyzing heat transfer of electronics, is being used as the simulation tool.
A diagram of the computed flow vectors in a plane parallel and adjacent to one of the VME boards is shown below. The flow shows large recirculation zones with very little air flow, which results in inadequate cooling of some components in these regions.
The simulation results are in general agreement with measurements on the actual system. Simulation models are now being used to study the effects of different chassis modifications to acheive more even air flow distribution. For more information, contact CALCE Center at (301) 405-5323.
Computed flow vectors of forced air over a VME board.
Using CALCE import/export utilities and Patran command language (PCL), the interface automatically exports the CALCE board model and constructs a Patran model. The model imported from CALCE is meant to be the first stage in a two stage modeling process.
In the first stage, components are represented by cuboids that model the dimensions of each individual part. In the second stage, areas of interest identified in the first stage, such as leads and solder joints, are modeled in more detail. Results derive d in the first stage are also used as boundary conditions for second stage analysis.
This technique limits the analysis scope to a manageable size and reduces required computer resources, while pointing out areas that warrant further investigation. For more information, please contact Michael Osterman at (301) 405-8023.
Display of finite element model created from CALCE to Patran interface.
