NASA and MacDonald Dettwiler, Space and Advanced Robotics Ltd. have turned to CALCE EPSC to assess the remaining life of the End Effector Electronics Unit (EEEU) in the robot arm of the Space Shuttle. The EEEUs have flown 102 missions over 20 years in all five of the United States space shuttles. The shuttle arm is used to place the satellites, space station equipment and other payloads into orbit. CALCE will use its product evaluation and qualification methods, called Virtual Qualification, to assess whether the system needs to be renovated, upgraded, modified, or discarded. For more information, contact Dr. D. Das at 301-405-5323.
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In October 2000, the CALCE EPSC Consortium initiated a comprehensive multi-year research effort to investigate the enablers for and the consequences of replacing the current binary Sn/Pb eutectic solder in electronics with the ternary Sn/Ag/Cu lead-free solder. The status of these projects is presented here.
Constitutive Behavior of Sn3.8Ag0.7Cu Solder: The experimental parameters for two constitutive models are being evaluated for the ternary Sn/Ag/Cu lead-free solder: (1) a partitioned constitutive model, where the elastic behavior is separated from rate-independent 'plastic', and rate-dependent 'creep' behavior; and (2) a unified creep-plasticity constitutive model. After reviewing several specimen configurations, a single lap-shear test configuration, based on the Iosipescu geometry, was chosen for the tests. This specimen configuration best mimics the geometrical constraints encountered at the solder/substrate interfaces in most electronic assemblies. A distortion-free and bending-free grip has been designed and evaluated to test these specimens in a micro-mechanical tensile tester (MTS Tytron) at ambient and elevated temperatures. Next year these measurements will be conducted on a binary Sn3.5Ag lead-free solder.
Durability Behavior of Sn3.8Ag0.7Cu Solder: The CALCE thermo-mechanical-microstructural (TMM) cyclic fatigue testing setup was modified to test at high temperatures, and to allow three different control modes: total strain range (TSR), inelastic strain range (ISR), and inelastic work (DW). Isothermal mechanical cycling tests have been conducted at two different temperatures (25°C
and 125°C), several different strain rates (from 1E-2 to 5E-4 s-1) and three different cyclic load levels. Rate-independent 'plastic' deformations dominate at low temperature and high strain-rate, while rate-dependent 'creep' deformations dominate at high-temperature and low strain rate. Plasticity-dominated tests were run on eutectic Pb/Sn and Pb/Sn/0.2Ag solders first for benchmarking purposes. Results reveal that the Pb-free solder is more durable than Pb/Sn eutectic solder for plasticity-dominated cyclic tests at 25°C. The ISR and DW tests provided comparable fatigue exponents for the load cases examined. The creep-dominated tests are in progress. In the future, we will conduct isothermal TMM tests on the Sn3.5Ag lead-free solder and also conduct thermomechanical cycling of lead-free electronic assemblies.
Influence of Board Plating on Intermetallic Growth in Sn3.8Ag0.7Cu Solder: The growth of intermetallics between Sn3.8Ag0.7Cu solder and printed wiring boards coated with either organic solderability preservative (OSP), immersion tin, immersion silver, or immersion gold over electroless nickel (ENIG) are being characterized. The effect of intermetallic growth on the bond strength at the plating/solder interface is being assessed. Boards with all four platings have been soldered and then aged at temperatures of 0.8 Tm (melt temperature), 0.85 Tm, and 0.9 Tm, for up to 1000 hours. Failures in ball shear tests have been in the bulk solder, instead of the intermetallic layers, for aging up to 100 hours. However, we have observed a slight decrease in the ball shear strength of the solder joints made to the ENIG and immersion silver platings. Aging beyond 1000 hours at 0.9 Tm results in failures due to high temperature degradation of the board laminate. With 1000 hours of aging at the lower two temperatures, failures occur in the solder or due to pad lift-off between the pad and the board. Current work involves cross-sectioning of the solder joints for microscopic and chemical examination. In the future work, we will characterize the thickness of the intermetallic layers to describe the growth kinetics, and to relate the intermetallic growth to the bond strength as appropriate.
Compatibility of Electronic Components with Sn3.8Ag0.7Cu Solder: Sn3.8Ag0.7Cu solder has a higher melt temperature (220°C) than Pb/Sn eutectic
solder (183°C). In order to investigate the effect of the higher reflow temperatures on component reliability, CALCE researched various lead-free reflow profiles and developed a composite profile from industry recommendations. The CALCE profile has a peak temperature of 260°C and duration of 80 seconds above
the lead-free melting point of 220°C. The reflow simulation equipment has been qualified for use in this profile. The upcoming experiments are focusing on CSP and BGA parts. An initial visual check and C-mode scanning acoustic microscopy (C-SAM) inspection will be performed on all samples. This will be followed by moisture sensitivity tests for tin-lead and lead-free profiles as per the J-STD-020-A methodology. Post-reflow non-destructive and destructive assessments will be performed on the sample components.
Solders are also used as a non-noble finish for some connectors. It is expected that lead-free solders will also be used for separable connector finishes. Determining the electrical characteristics of the lead-free solders as a surface finish is crucial. We are examining the effects of aging on contact resistance of lead-free solder coating compared with tin lead solder coating under high temperatures. Fretting behavior will also be investigated and compared to the currently used tin and tin alloy systems.
Tracking of Lead-Free Mandates: Among the environmentally friendly electronics issues, the elimination of lead from electronic products is getting the most attention. For over a year, CALCE has been tracking the legislative and consumer agendas on the elimination of lead from electronic products. In this review, selected electronic product types at each stage of design, manufacture, use, and disposal, are being examined. Several trends are already visible in this regard. Market issues are found to have the most direct effect on the introduction of lead free products. In spite of the difficulty in selecting the specific lead free solder alternative, several Japanese companies have already introduced lead-free products into the market. Judging from the lead-free rollout date of different companies, the emergence of lead-free products is likely to beat the clock of legislation and regulations. On the other hand, the environmental impact of going lead-free, such as air pollution due to increased energy use, is also being vigorously discussed and debated. The final report of this project will include a status of the green electronics movements and the company roadmaps on lead- free product introduction.
For more information on the lead-free projects, contact Dr. A. Dasgupta at dasgupta@calce.umd.edu, Dr. M. Pecht at pecht@calce.umd.edu, Dr. B.T Han at bthan@calce.umd.edu, Dr. P. McCluskey at mcclupa@calce.umd.edu, Dr. D. Barker at dbarker@calce.umd.edu or Dr. D. Das at
digudas@calce.umd.edu.
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Using calcePWA software, Honeywell in collaboration with CALCE EPSC performed a virtual qualification on the AS900 engine control module. As a result, Honeywell avoided a costly design deficiency early in the product development phase. The calcePWA simulation indicated that some parts had inadequate interconnect durability to be considered for the application environment. Subsequent physical testing verified the simulation results.
Virtual Qualification involves the application of simulation techniques to assess the life expectancy of a product under anticipated operational loading conditions. It also allows designers to identify design deficiencies early in the design cycle and to perform trade-off and sensitivity studies for the determination of critical design parameters. Such simulation can be further used in the development of physical tests. The physical tests in turn can be used to demonstrate that the simulation accurately models the physical hardware. The physical tests can also be used to further reduce the chance of a design defect or deficiency escaping the design process.
Over the past several years, CALCE EPSC working with major electronic hardware manufacturers has developed software and methodologies to assist in accelerating product development and qualification. These efforts have successfully demonstrated the use of virtual qualification as part of an overall Physics of Failure approach to ensuring product reliability.
Virtual Qualification Application. In the Honeywell electronic hardware assessment, the qualification process required approximately one month to complete. It involved developing the simulation model, including anticipated life cycle loading scenario, simulating the response of the hardware to the life cycle loading conditions, and conducting failure assessment based on failure mechanisms induced by the anticipated life cycle loading. The model development process was simplified because calcePWA directly imported design data from Honeywell designs, developed using Mentor Graphic's Board Station software.
Life Cycle Load Characterization. The life cycle loads were provided by Honeywell and were taken from sensors located in the expected use environment. The life cycle loading scenario included temperature cycling and vibration.
Stress Assessment. Using the calcePWA software, the component and board temperatures were evaluated based on the life cycle loading scenario. Power dissipation rates of the components on each Circuit Card Assembly (CCA) were derived from electrical simulation performed by the CCA design team. Simulation results indicated a maximum of 12°C rise over boundary conditions for the three CCAs. The response to vibration was also characterized.
Failure Assessment. Relevant failure mechanisms were identified and evaluated based on the design and the life cycle loading scenario. Results indicated that interconnect durability of a ceramic oscillator would not meet the desired life expectancy. Other parts were also found to have inadequate design life.
Physical Verification. Thermal simulation was verified using physical prototypes. These prototypes were electrically powered and component temperatures were measured with thermal couples. A comparison of simulated and experimental measurements indicated excellent agreement.
To verify the failure assessment results, a prototype was subjected to a temperature cycle of -50°C to 125°C with the complete cycle lasting 45
minutes with 10-minute dwells. Simulation of this stress condition indicated
a life expectancy of less than 300 temperature cycles for the ceramic oscillator. The results of the test closely matched the simulation results. A cross-section of one of the solder joints of the ceramic oscillator after 300 temperature cycles (picture below) shows that the interconnection has completely failed.
Based on the calcePWA assessment, Honeywell has implemented parts changes and other improvements to the design.
To obtain further details or to discuss software solutions for virtual qualification or performing virtual qualification on your products, contact Dr. Michael Osterman at 301-405-5323 or email osterman@calce.umd.edu
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Since their introduction in the late 1990s, surface mount multilayer ceramic capacitors (MLCCs) gained rapid acceptance by the electronics industry and today are among the most common components on a circuit card assembly. The reliability of an MLCC can be extremely high, with an expected operating lifetime of decades. Problems occur when defects are introduced, either during manufacture or the assembly processes. Due to the large amount of energy stored by capacitors, internal shorts resulting from defects can cause explosions and dramatic temperature increases, which not only destroy the MLCC, and any evidence of root cause, but can also damage surrounding components, the printed board, adjacent circuit card assemblies, and may even lead to fires. Over the last eighteen months, CALCE laboratory services have assisted a number of companies in finding MLCC root cause failures.
Failure Analysis. When MLCC failure is catastrophic, the failure investigation starts by examining the MLCCs adjacent to the failure site and those in the same failure area on similar circuit card assemblies.
The first step in the failure analysis (FA) process is to confirm that electrochemical migration (ECM) underneath the capacitor was not the root-cause of failure. If samples of non-catastrophic failures exist, ECM can be investigated by washing the area around and underneath the capacitor and examining the solution for high levels of chlorides or bromides. Once ECM has been ruled out, the MLCCs are examined using scanning acoustic microscopy (SAM), with a 110 MHz transducer. This is very effective in locating voids, delaminations, and horizontal cracks, although it is not as successful in identifying flex cracks, thermal shock cracks, or other types of vertical cracks causing MLCC failures.
Flex cracks and extensive thermal shock cracks can be identified through methanol testing. Due to its polar nature, methanol is an electrically conductive liquid. Capillary action and methanol's low viscosity allow methanol to become quickly absorbed by any surface cracks present in the capacitor. If the crack has propagated across opposing electrodes, the absorbed methanol will temporarily form a conductive film between the two electrodes, creating an observable rise in current leakage.
All suspect capacitors are eventually subjected to cross-sectioning. This is because some defects, such as small thermal shock cracks and vertical cracks caused by poor handling, are otherwise hard to detect. Cross-sectioning can be performed on capacitors attached to the board or on single capacitors. Sectioning of the board can create additional defects in the capacitor and confuse the FA process, so care must be taken. Air can also become trapped between the capacitor and the board during the potting process leading to damage during grinding and greater difficulty in getting an optimum image.
MLCCs can be removed from the board, preferably with a 150°C preheat and with hot air, to prevent the removal itself from introducing a defect and confusing the FA process. Next, the MLCCs are labeled so that top/bottom and left/right directions are identified, and then mounted in room-temperature cure epoxy for ease of handling and to minimize damage during cross-sectioning. For maximum efficiency and minimum damage, MLCCs are ground using 600-, 800-, and 1200-grit silicon carbide paper and periodically checked for anomalies. Beginning with a fine grit greatly reduces the amount of grinding-induced porosity that can mask intrinsic porosity, small cracks, and delaminations.
Thorough examination is conducted on at least four different internal planes--preferably where the end cap is ground off, at the start of the internal electrodes, and two other cross-sections. Optical examination is performed at magnifications between 50x and 200x. For maximum contrast, images are taken in bright and dark field modes. A particular emphasis is placed at the termination of the end caps, since this is where flex cracks and thermal shock cracks initiate.
Identification of Root Cause. Failures of MLCCs are often accelerated by defects introduced during the capacitor manufacturing process or by excessive stresses experienced at various stages of assembly. During manufacture, failure accelerators can arise from different root-causes. Contamination in the ceramic powder can lead to excessive porosity or voids. A void bridging electrodes can become a short leakage current path and a latent electrical defect. Non-optimized pressing or sintering can also lead to excessive porosity and voids, and to delamination (knit line cracks). Delaminations and single-layer voids do not cause failures directly but are very sensitive to mechanical stress that can rupture inter-electrode dielectric layers, which then become the latent leakage paths. Delamination can also extend from an electrode end to the opposite termination, again causing a latent leakage path. Rapid cooling can cause firing cracks, which often originate at an electrode edge, but not always. A firing-crack propagation path is perpendicular to the electrodes.
The danger of forming cracks, even microcracks, during the placement step is that the high temperatures during soldering will often induce internal cracks to grow across several electrodes. Cracking due to excessive placement force by a vacuum tweezer primarily consists of surface damage on the top of the MLCC with the potential for microcracking on the board side of the component.
Centering jaws can cause cracking due to excessive force or worn bits leading to stress concentrations. Both root-causes leave distinct crack signatures.
MLCCs are sensitive to thermal shock due to their construction and to differences in the CTEs of the materials used. Thermal shock cracks can occur during solder reflow, wave solder, cleaning and rework. Thermal shock cracks generally initiate on the bottom-side of the capacitor, at the termination of the end cap. They often propagate at a 45-degree angle and tend to range in size from 10 to 500 microns.
Capacitor failures that occur during connector insertion, depaneling, or bolting are often due to excessive flexure. Excessive flexure can cause flex cracks, which can emanate from the termination of the end cap and propagate at a 45-degree angle. This is similar behavior to a thermal shock crack. The primary difference is the size; flex cracks tend to be larger, propagating through the ceramic until the crack reaches the end cap.
For more information on ceramic capacitor failure identification and corrective actions, contact Dr. Keith Rogers of CALCE Laboratory Services at 301-405-4316 or email krogers@calce.umd.edu.
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CALCE EPSC in collaboration with Sandia National Laboratories, Siemens, and Grundfos, has conducted a review of failure mechanisms and materials related to microelectronics. This effort has resulted in software updates that have been included in the recent release of version 2.6 of CADMP-II software, available to all members. The software comes with a validation guide, a tutorial, a list of attributes and their sources, and a database of JEDEC package styles with associated material and geometric parameters.
The software provides the user with the opportunity to utilize well-accepted and recognized models from published literature in order to conduct a rapid reliability assessment of microelectronic component designs. Considerable effort has been expended to ensure that the failure mechanism models and material properties have been properly applied from the original references, and that the software performs accurate calculations using these models.
For more information, contact Dr. Patrick McCluskey at mcclupa@calce.umd.edu.
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A web-based software tool for the application-specific assessment of embedded passive technologies has been jointly developed by the NIST Advanced Embedded Passives Consortium and CALCE EPSC. This software delivers an application-specific economic analysis of the conversion of discrete passive components (resistors and capacitors) to integral passives that are embedded within a printed circuit board. It performs three analyses: 1) Board size analysis is used to determine board sizes, layer counts, and the number of boards that can be fabricated on a panel; 2) Panel fabrication cost modeling includes a cost of ownership model to determine the impact of throughput changes associated with fabricating integral passive panels; and 3) Assembly modeling is used to determine the cost of assembling all discrete components, and their associated inspection and rework.
The tool is available to CALCE Consortium and NIST Advanced Embedded Passives Consortium members at: here. For more information, contact Dr. Peter Sandborn at sandborn@calce.umd.edu or call 301-405-3167.
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The fundamental physics of the PDP technology was first introduced more than thirty years ago, yet PDP commercial products have emerged only recently. The PDP offers numerous unique advantages over conventional display products such as the cathode ray tube (CRT) and liquid crystal display (LCD). The PDP has virtually no limitation in size. With the current technology, PDPs can be as large as 80 inches, substantially exceeding the limits of LCD technology, while keeping the thickness and weight an order of magnitude smaller than the CRT. Other advantages include wide viewing angle, good uniformity, and no magnetic field distortion. With a high resolution and rapid signal processing capability, the PDP has become an optimal choice for the future high definition multi-media display products.
This year, CALCE has initiated a research effort in PDP technology focused on the key technical challenges encountered in their manufacture and operation. The goal is to develop methodologies, strategies, and a knowledge base for current and future PDP technology and thus to improve the time-to-profit for competitive PDP products. Several research projects are being conducted to achieve this goal. They include: PDP material characterization, stress optimization for manufacturing process, structural design guidelines for enhanced mechanical reliability, thermal management solutions for optimum operating conditions, and accelerated durability assessment for life prediction.
For more information, contact Dr. Bongtae Han at 301-405-5255 or Dr. Miky Lee at 301-405-5323.
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Work has begun on the construction of a pre-compliance anechoic chamber that will enable CALCE EPSC to expand its electromagnetic testing capabilities into the GHz range. The anechoic chamber will allow testing of products as if the product is present in isolation from any other electromagnetic source. In analogy, the anechoic chamber is equivalent to the clean room in solid-state circuit fabrication.
The new chamber, which will be used to support EMI/EMC research, will measure 25 ft x 11 ft x 10 ft and will have EMI/EMC testing capabilities covering the 80 MHz to 20 GHz frequency range. CALCE EPSC is grateful to IBM for its generous donation of part of the electromagnetic absorbers. The IBM donation totals $15,000 in value.
Present research in the CALCE EPSC Electromagnetic Compatibility and Propagation Laboratory (EMCPL) lead by Dr. Omar Ramahi is focusing on power plane modeling in printed circuits. Novel techniques are being developed to reduce ground bounce noise in printed circuit boards as well as to mitigate EMI/EMC effects due to high-speed digital switching. At the chassis level, efforts are under way to study fundamentals of radiation from ventilation apertures and gaskets.
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