E-SEM Image of a Hollow Fiber
In recent months, CALCE EPSC Director Prof. Michael Pecht has received letters from an Intel attorney and the president of the Semiconductor Industry Association discouraging CALCE EPSC from offering its uprating course. The implication is that CALCE EPSC may be construed to be encouraging an unsafe practice by discussing uprating.
In the mid-1990s, Prof. Pecht found that electronics were being used outside the datasheet specifications in underhood automotive, avionic, oil well, and military applications. For example, the Boeing 777 has numerous parts used outside datasheet specifications. In 1997, Prof. Pecht coined the word "uprating" to define a process to assess the capability of a part to meet the functional and performance requirements of an application in which the part is used outside the manufacturers' specified temperature range. Since that time, Prof. Pecht and CALCE EPSC have been conducting pioneering research in all aspects of uprating including: developing uprating methods; validating the methods with case studies; working with the electronics industry supply chain and regulators in developing industry guidelines; and investigating the legal and business issues associated with uprating.
The uprating challenge arises because today's semiconductor parts are most often specified for use in the "commercial" 0 to 70oC, and to a lesser extent in the "industrial" -40 to 85oC operating temperature range. There is demand for parts rated beyond the industrial temperature range, primarily from the aerospace, military, oil and gas exploration, and automotive industries, but the demand is often not large enough to attract the major semiconductor part manufacturers to make them. In fact, wide temperature range parts are becoming obsolete.
CALCE EPSC now has a state-of-the-art knowledge repository on uprating. This includes information on datasheets, ratings and specifications, over 20 CALCE EPSC technical articles, references to most other uprating related documents and numerous case study descriptions, and a description of uprating methods.
Prof. Pecht has responded to both Intel and the SIA, and he encouraged more communications and cooperative research. Uprating is here to stay and it is important that the techniques and issues are openly discussed. For further questions, contact Prof. M. Pecht at pecht@calce.umd.edu.
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The Schlumberger (an oil well service company) Reservoir Completions Center has turned to CALCE EPSC to provide an independent assessment of the reliability of their Hyper Permanent Quartz Gauge's (HPQG - rated to measure temperatures up to 175°C and pressures up to 20,000 psi) electronics in a joint project with BP (an oil exploration and production company), to assess and optimize the reliability of electronic gauges, which are permanently installed in deep hot wells. These gauges sense the temperature and pressure downhole during oil extraction helping petroleum engineers to optimize the production and ultimate recovery of the resource, to extend the lives of oil wells, and to reduce risks and uncertainties. Once installed, it is not practical to recover these electronics for maintenance or repair, hence their design, manufacturing, transportation, storage, installation and use need to be assessed for their impact on reliability to ensure failure-free operation for the life of the oil well. CALCE EPSC will use virtual qualification computer analysis complemented by accelerated laboratory testing to determine the reliability of the HPQGs under the harsh conditions they must endure downhole. For more information, contact Dr. Diganta Das at digudas@calce.umd.edu.
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A large number of infant mortalities in electronic products today can be traced back to the manufacturing of the printed circuit board (PCB). However, the current methodology to assess and manage printed circuit board suppliers is often either subjective, based on internal specifications, or outdated, relying on the inactive document MIL-PRF-55110. CALCE EPSC has been developing strategies to assess a contract PCB fabricator that will lead to cost savings while still ensuring a quality supplier.
Selecting and managing a printed board supplier is a five-step process, involving metric identification, surveying, auditing, qualification, and tracking. CALCE EPSC has identified fourteen vital metrics in the assessment of contract manufacturers. These include financials, technology, corporate business plan, geography, dependability, flexibility, quality, customer service, competitiveness, logistics, supply chain management, labor force quality, e-commerce, and security.
When surveying board suppliers, IPC-1710: The OEM Standard for Printed Board Manufacturers' Qualification Profile should be used. Some OEMs, especially in aerospace and military applications, still use inactive QPL-55110 in their selection process. While IPC-1710 is widely used, it is not always comprehensive. When used in conjunction with the IPC-1710 surveys, the CALCE EPSC review helps narrow the group of suppliers selected for audits and helps assess the results of on-site audits.
Once the survey forms are received, review them to ensure that your product requirements match the supplier's capability. Other checks should include determining whether the board supplier does fine-line artwork or has experience with high-voltage boards. When possible, use the IPC specifications, thereby specifying product requirements.
After the number of potential board suppliers has been reduced, start planning the audit. Audits can be conducted off-site, on-site, or both. One efficient off-site audit is to send prospective board shops a test design with known defects, then track where and how successful the shop is in identifying the defects. An additional off-site audit can be conducted by identifying two to five parameters, such as solder mask thickness, that are critical to product functionality and reliability. The manufacturer should be able to prove that these parameters are under statistical process control (SPC) over some time period, typically two weeks. The on-site audit should include requesting the following documents: the product parameter document; a control plan (including all processes); examples of actual control charts; examples of actual rework documents and analysis charts; examples of actual scrap analysis documents; and examples of maintenance records. The actual audit should focus on your specific products. The number of suppliers to be audited rarely exceeds six and should include at least two. An efficient method of product qualification is to select a PCB fabricator that has qualified a similar product to a similar environment.
The final step in the supplier selection process is tracking. Root-cause failure analysis must be conducted on all quality and reliability fall-outs. When encountering a poor PCB supplier, selecting an alternate supplier may be less costly.
For further inquiries, contact Dr. Michael Osterman at 301-405-8023 or osterman@calce.umd.edu.
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The rapid growth of the electronics industry has spurred dramatic changes in electronic parts. Increases in speed, reductions in feature size and supply voltage, and changes in interconnection and packaging technologies are becoming events that occur almost monthly. Consequently, many of the electronic parts that comprise a product have life cycles that are significantly shorter than the life cycle of the product. This life-cycle mismatch problem requires that during design, engineers be cognizant of which parts will be available and which parts may become obsolete during a product's life. The problem is especially prevalent in avionics and military systems, where systems may encounter obsolescence problems before being fielded and nearly always experience obsolescence problems during their field life. Manufacturing that takes place over long periods, and the high cost of system requalification that makes design refreshes extremely expensive, exacerbate the problem.
Many part obsolescence mitigation strategies exist, including life-time buy, last-time buy, part replacement, aftermarket source, uprating, emulation, re-engineering, salvaging, and redesigning of the system.
Redesign (or design refresh) is the ultimate obsolescence mitigation approach where obsolete parts are designed out of the system in favor of non-obsolete parts. Nearly all long field life systems are redesigned one or more times. Unfortunately, design refresh potentially has large non-recurring costs, and it may require costly requalification of the system. Therefore, design refreshes are not a practical solution every time a part becomes obsolete and must be prudently planned.
A methodology has been developed for determining the part obsolescence impact on life-cycle sustainment costs for long field-life electronic systems, based on future production projections, maintenance requirements, and part obsolescence forecasts. Based on a detailed cost analysis model, the methodology determines the optimum design refresh plan during the field-support life of the product. The design refresh plan consists of a number of activities, their respective calendar dates, and content aimed at minimizing the life-cycle sustainment cost of the product. The methodology supports user-determined short- and long-term obsolescence mitigation approaches on a per-part basis and variable look-ahead times associated with design refreshes, and allows for inputs to be specified as probability distributions that can vary with time. Outputs from this analysis are used as inputs to the PRICE Systems PRICE H/L commercial software tools for predicting life-cycle costs of systems.
The Mitigation of Obsolescence Cost Analysis (MOCA) software tool was developed by the Physics of Failure Approach to Sustainable Electronic Systems (PASES) program. PASES is a U.S. Air Force ManTech program involving the University of Maryland, Honeywell and Price Systems. Currently, CALCE is extending MOCA capabilities, and preparing it to be released to the CALCE Consortium membership in spring 2002.
For more information on and availability of the MOCA software tool, please contact Dr. Peter Sandborn at 301-405-
3167 or sandborn@calce.umd.edu.
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Fiber optic technology has made a very rapid transition from the research and development stage into practical application. The advantages of using optical fiber instead of copper wire are: enormous potential bandwidth, small size and weight, electrical isolation, immunity to interference and crosstalk, signal security, low transmission loss, ruggedness and flexibility, system reliability and ease of maintenance, and potential low cost. Because of these advantages, optical communication systems are introduced widely into telecommunication networks, computer networks, and military applications.
In the telecommunications industry, the traditional approach to reliability assessment is to use SR-332, Telcordia's reliability prediction handbook. This takes on critical importance for light emitting diodes (LEDs) and laser diodes (LDs), since they tend to dominate the reliability of optical communication systems. Unfortunately, the failure data from SR-332 for these optoelectronic devices is often of questionable value because there is a significant time delay acquiring field data while the industry experiences rapid design and material changes and improvement in manufacturing processes. In addition, the typical failure mode of LEDs and LDs is a gradual degradation of the power output over time, while SR-332 provides information only in terms of a steady-state failure rate.
Users of LEDs and LDs should define the power output that would result in failure in their system and then use physics-of-failure (PoF) models to predict time to failure. The definition of failure is critical, because when an optoelectronic device is considered to have failed varies among manufacturers and users. One method of determining failure is to hold the driving current fixed and to define the end of life as that time when the output power falls below a certain percentage, often 20 to 50 percent. Another method monitors the output power and, as the power starts to fall, adjusts the drive current to a larger value required to maintain the original power level. When the drive current reaches a predetermined relative value (e.g., 50 percent increase), the device is considered to have reached the end of a useful life.
The following describe the failure mechanisms and defects that can initiate failure in LEDs and LDs and demonstrates how focusing exclusively on the impact of temperature and current density can lead to invalid product qualification.
Active Region Degradation. The active region is where light is emitted by radiative recombination of injected carriers. Degradation of the inner region is caused by the nucleation and growth of dislocations and the precipitation of host atoms. These processes require the presence of a crystal defect and are accelerated by injected current density, joule heating by injected and ambient carriers, and emitted light. Material selection also has an effect, as AlGaAs/GaAs is much more sensitive to this mechanism than InGaAs(P)/InP.
Electrode Degradation. Electrode degradation occurs in both LEDs and LDs. Degraded electrodes generally correspond to p-side electrodes because ordinary devices are composed of n-type substrates and the p-side electrodes exist near the active region of these devices. For devices with a p-type substrate, the corresponding electrode is the n-side electrode. Electrode degradation is mainly caused by metal diffusion onto the inner region or so-called outer diffusion of semiconductor material. This diffusion will increase as the injected current and ambient temperature increase.
Facet Degradation is a serious problem in AlGaAs/GaAs LDs emitting visible light, but is not an issue in nominal LEDs or InGaAsP LDs. Oxidation through a photo-assisted reaction at the facet leads to increased threshold currents, thus reduced laser lifetimes. Another mode of facet failure is catastrophic optical damage (COD). When light output power exceeds a critical level, the facet melts. Handling damage and contamination can initiate failure in optoelectronic devices even for products that are resistant to facet degradation.
Thermal Runaway. The amount of heat generated during operation requires LEDs and LDs to be bonded to a heatsink or substrate, often through the use of a solder attach. If the thermal path is insufficient, often due to the presence of voids in the solder attach, hot spots will arise. This will eventually lead to thermal runaway and failure. Thermal runaway due to solder voiding often dominates failure occurrences in LDs within 10,000 hours of operation. Voiding can occur due to poor processing conditions or metal diffusion at the interface (i.e., Kirkendall voiding).
Voiding can also initiate due to electromigration. When a sufficiently high current density is available in the metal, vacancies and metal ions will migrate towards opposite poles, leading to void formation, hillocks and whiskers. Whisker growth, which is influenced by internal strain, temperature, humidity, and material properties, is usually observed near the bond between the solder and the heatsink and can lead to electrical short circuits.
Electrostatic Discharge (ESD). Semiconductors are sensitive to damage by ESD. The failure modes due to ESD can be sudden failure, parametric shifts, or latent damage that can lead to degradation during subsequent operation. According to MIL STD 883-Method 3015, the sensitivity of semiconductor lasers to ESD damage should be greater than 100V on the "human body model" test.
Thermal Fatigue. When the coefficient of thermal expansion between bonded parts and the bonding solder does not match, stresses are introduced during temperature cycling in the manufacturing process. This can cause delamination between the attachments. When power devices (including laser diodes) undergo cycling stress, different performance of hard-soldered and soft-soldered devices has been reported. Thermal fatigue is observable in soft solder, while hard solder is stable against thermal cycle stressing.
Although LEDs or LDs degrade gradually in most cases, sudden failures have been observed due to dislocation growth from outside the active regions, p-n junction destruction, dislocation growth from the facet oxidation region or the interface between the facet and the dielectric coating film, and catastrophic optical damage.
For more information on failure mechanisms in light emitting diodes and laser diodes or CALCE EPSC research in optoelectronics, contact Dr. Michael Osterman at 301-405-8023, email: osterman@calce.umd.edu, or Dr. Don Barker at 301-405-5264, email: dbarker@calce.umd.edu.
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Increases in failures due to internal board shorting by conductive filament formation (CFF) have driven glass and laminate manufacturers to consider screens and qualification tests to assess the hollow fiber concentration of circuit cards.
Laminates composed of hollow fibers pose a threat to the reliability of electronic systems in that they provide a convenient open path for CFF. CFF, also referred to as metallic electromigration, is an electrochemical process. This process requires, as do all other migration phenomena, the transport of a metal through or across a nonmetallic medium under the influence of an applied electric field. CFF is difficult to detect in the field because once it occurs, sufficient heat is generated to "vaporize" the conductive filament and "clear" the failure. Furthermore, observation of a partial filament requires destructive analysis. The most apparent solution for the elimination of hollow fibers is to improve manufacturing processes and controls.
Multi-layer organic laminates, which make up over 90 percent of the present types of interconnecting substrates in today's electronics (standard FR-4 represents 85 percent of resin systems), can develop a loss of insulation resistance between two biased conductors due to the CFF phenomenon. The opportunity for failure due to CFF is a function of temperature, moisture content, the voltage bias, and manufacturing conditions.
E-SEM Image of a Hollow Fiber
Based on CALCE EPSC's recommendations, hollow fiber assessment has now become a standard screen by some board fabricators and contract assemblers to qualify suppliers and discard lots with hollow fiber concentrations above specifications. The CALCE EPSC specification being used by laminate manufacturers for this screen is no more than one hollow fiber per 10 cm x 10 cm. This guideline specification reduces the CFF opportunity to less than 1 percent, based on calculations done at CALCE EPSC. As a result of CALCE EPSC's efforts, Nan Ya Plastics, one of the world's largest glass fiber manufacturers, revised their glass production process and experienced a sharp drop in hollow fiber concentration.
For more information on hollow fibers and conductive filament formation, contact Dr. Keith Rogers at 301-405-5316.
With ever finer area-array interconnect spacing and flip-chip packages with smaller profiles, control of underfill properties and processing parameters becomes more important to satisfy the needs of current and new technologies. Determination of appropriate mold compounds for flip-chip technology would provide a controllable, variable process for a more reliable package. The interplay between the chip size, pitch, the filler type, and size distribution (especially issues of nanoparticles) must be examined in a structured manner to understand its effects on final properties.
The initial goal is to identify particle variations and how they relate to property variations, and ultimately to develop feed protocols to ensure consistent filler-molding compound distributions that result in constant physical properties. Developing general rules for feed protocols to control filler distributions leads to the concept of functionally graded materials (FGMs), defined as components with engineered gradual transitions in microstructure and/or composition that optimize functional requirements that vary with location within the component. Of primary interest are requirements involving thermal, mechanical, and electrical behavior, such as smart structures and electronic packaging.
In developing FGMs, there are two major common problems. The first involves the development of appropriate processes for fabricating the structure. The second is determining the optimal graded architecture for the structure. Resolving these problems requires a multidisciplinary approach that utilizes an understanding of materials science and mechanics. The Japanese have proposed such an approach, termed the "inverse design procedure". In this approach, component design and fabrication are synergistically combined, not just for manufacturing FGMs, but also to establish an entirely new approach to engineering structures.
Faculty and research staff at the University of Maryland have been developing inverse design procedures for a wide range of applications, including new energetic materials with tailored burn rate performance, smart thin films with improved frequency response, and advanced metal-ceramic structures with improved fracture toughness. At the core of this development effort are novel design, fabrication, characterization, and modeling technologies that are applied at length scales ranging from nanometers to millimeters. For example, a material gradient optimization method has been developed that combines genetic algorithm optimization techniques with finite element modeling to design optimal graded structures. Finally, the thermal and mechanical behaviors of these FGMs are being characterized by combining a digital image pattern recognition technique known as digital image correlation with scanning probe microscopy, and thermal imaging. This approach is an exciting idea to apply to appropriate electronic packaging applications.
For more information on molding compounds for flip-chip devices or current research in this area at CALCE EPSC, contact Dr. David Bigio at 301-405-5258 or email bigio@eng.umd.edu.
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In November of 2001, CALCE EPSC and the City University of Hong Kong agreed to conduct joint research and collaborate on the development of tools and methodologies in the field of electronic product failure analysis. This agreement emphasizes the importance of international scientific collaboration in advancing the state of the art in electronic product failure analysis tools and methodologies. As part of the effort, both institutions will engage in joint research and development projects, temporary exchange of staff and students between their respective laboratories, and exchange of scientific information, research results and academic materials.
Benefits of this unique partnership to the members of the CALCE Consortium include field support to companies manufacturing in S.E. Asia, City University technicians trained at CALCE EPSC to understand CALCE processes and methods, and joint research ventures capitalizing on the strengths of these two world-renowned organizations.
For further information, please contact Prof. M. Pecht at pecht@calce.umd.edu.
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IEEE Standard 1413, "IEEE Standard Methodology for Reliability Prediction and Assessment for Electronic Systems and Equipment," provides a framework for reliability prediction procedures for electronic equipment at all levels. A new document, IEEE 1413.1, "Guide for Selecting and Using Reliability Predictions based on IEEE-STD 1413," is being developed as a supporting document for IEEE Standard 1413. It describes a variety of hardware reliability prediction methodologies.
The purpose of the guide is to assist in the selection and use of reliability prediction methodologies satisfying IEEE Standard 1413. The guide accomplishes this purpose by briefly describing reliability prediction methodologies with the objective of providing information to make an informed decision as to whether to pursue a particular prediction methodology for a particular application. It will also help the readers assess reliability prediction methodologies that they use as per IEEE 1413 criteria. The reliability prediction methodologies discussed and assessed include prediction using field data, test data, stress and damage models, and handbook methods. Users and developers of the different methods participated in the committee that prepared the document.
CALCE EPSC has taken a leadership role in the development of this guidebook. Prof. Michael Pecht serves as the chairman of the committee developing the guide and Dr. Diganta Das serves as a lead member. The involvement of CALCE EPSC has ensured that the guidebook includes science-based reliability prediction methodologies. CALCE EPSC has also provided critical and independent evaluation of all the methodologies. CALCE EPSC continues to work with the telecommunications industry to assess their reliability prediction methods, in particular the use of Telcordia SR332 in predicting reliability.
Contact Prof. M. Pecht at pecht@calce.umd.edu or Dr. D. Das at digudas@calce.umd.edu for more information.
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