Over the last year, CALCE EPSC has conducted more than 200 reliability analysis investigations and assessments for over 100 electronics companies using our expertise and our state- of-the-art equipment and virtual qualification and reliability assessment software. Our research in physics-of-failure has enabled us to advance electronics design, accelerated testing, life consumption monitoring, supply chain management, reliability assessment of MEMS (MicroElectroMechanical Systems) technology, design for electromagnetic compatibility, and the assessment of reliability risks in using environmentally friendly materials, such as lead-free solders.
Today, the Center has an established process for accelerated life-cycle testing, which enhances the traditional HALT (Highly Accelerated Life Test) methodologies for electronic parts and assemblies. CALCE EPSC accelerated test methods can effectively put an equivalent year of field wear on an electronic product in just a few days or weeks and provide estimates of useful life.
State-of-the-art laboratories and equipment at CALCE EPSC offer the latest failure detection and materials characterization techniques. For example, CALCE EPSC researchers have used scanning SQUID (Superconducting Quantum Interference Device) microscopy to locate previously undetectable sites of short circuits in advanced (low voltage, high density, thin layers) printed circuit boards. We also developed advanced moir?interferometry equipment and techniques to assess micro-structures and to separate the effects of dimensional changes induced by temperature and moisture changes in microcircuit encapsulants and underfills. Physics-of-failure software developed at the Center is being widely used outside the Center for virtual qualification, reliability assessment and accelerated test planning. For example, NASA has recently used CALCE software to assess the state of the aging space shuttle fleet, and Honeywell used CALCE software in the reliability assessment of the electronics in development of the AS900 aircraft engine control system.
CALCE EPSC was established to meet the needs of a growing electronics design and manufacturing industry and can readily offer the latest resources and tools to help engineers assess, mitigate and manage risks in electronic products. Our goals are straightforward: to offer the highest quality research environment to the electronics industry; to provide the world's best knowledge base for building reliable, competitive electronic products; and to educate the next generation of leaders and engineering professionals who will carry the CALCE EPSC methodology and research to a higher level.
If your organization is interested in utilizing CALCE EPSC expertise and resources, you can contact me, Professor Michael Pecht or visit our website.
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With clock speeds reaching well into the microwave region, circuit boards and interconnects become highly efficient radiators. This, unfortunately, leads to the emission of electromagnetic noise that can cause appreciable interference with other devices. The problems of electromagnetic interference (EMI) and electromagnetic compatibility (EMC) have been recognized as major reasons for product delay and costly redesigns. Recognizing the importance of meeting EMI/EMC requirements during the design cycle, CALCE EPSC has developed a state-of-the-art testing facility to address the variety of testing scenarios needed to ensure pre-compliance with government and corporate standards.
The recently completed facility is fully equipped to test circuit boards and antennas used in wireless applications. It includes a 25 ft anechoic chamber capable of testing from 20 MHz up to 20GHz, an Agilent PNA-series Vector Network Analyzer (26MHz to 50GHz) with 2.4 mm test set, an EMC Spectrum Analyzer (up to 26GHz), a Source Generator/Synthesizer, an Agilent Infinium Oscilloscope (600MHz), and the High-Frequency Spherical Dipole Radiator for calibration and shielding studies, amongst various low-and high-frequency probes and antennas.
Detailed information is available through Dr. O. Ramahi or at the website.
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In October 2000, the CALCE EPSC Consortium initiated a comprehensive multi-year research effort to investigate the enablers for and the consequences of replacing the current binary Sn/Pb eutectic solder in electronics with lead-free solders. The status of the current projects is presented below.
Constitutive Behavior of Sn3.5Ag Solder: The constitutive properties of a binary lead-free solder Sn3.5Ag, recommended for wave soldering by NEMI, are being evaluated. Constant load and constant strain rate tests are performed at various temperatures and the constants of a unified creep-plasticity constitutive model are determined from the experimental data. A modified single lap-shear test configuration, based on the Iosipescu geometry, is used for the tests. A novel extended structure has been developed to improve the accuracy of measurement. The extension is attached directly to the specimen and it converts a shear displacement to an axial displacement, which is subsequently captured by a high-resolution extensometer. With aid of the structure, shear deformations are measured without compensating machine and grip compliance, which enhances the accuracy of measurement significantly. In addition, the specimen configuration includes geometrical constraints at the solder/substrate interfaces in most electronic assemblies.
Durability Behavior of Sn3.8Ag0.7Cu and Sn3.5Ag Solders: The durability team has continued to study the cyclic mechanical and thermo-mechanical durability of the SnAgCu and SnAg solder systems, based on NEMI recommendations. The findings do not corroborate the claims of many investigators that the lead-free solders are at least as durable as SnPb solders. On the contrary, we find that for some loading situations, the lead-free solders are in fact less durable. Furthermore, for accelerated testing, we find that the acceleration factors are quite different from SnPb solders, both for thermal cycling as well as for mechanical cycling.
Influence of Plating on Intermetallic Growth in Sn3.8Ag0.7Cu Solder: The growth of intermetallics between Sn3.8Ag0.7Cu solder and printed wiring boards coated with either organic solderability preservative (OSP), immersion tin, immersion silver, hot air leveled solder (by an HASL process), and immersion gold over electroless nickel (ENIG) has been characterized. The effect of intermetallic growth on the bond strength at the plating/solder interface has also been assessed for boards with all five platings after reflow soldering followed by aging at temperatures of 0.8 Tm (melt temperature), 0.85 Tm and 0.9 Tm for up to 1,000 hours. Bond shear testing has resulted in failures in the bulk solder for all coatings except HASL, where Pb in the plating weakened the interface near the Cu6Sn5 intermetallic. Current efforts focus on durability testing of the plating/solder interface and on intermetallic formation at the component finish/solder interface.
Tracking of Lead-Free Mandates and Industry Readiness: CALCE EPSC has been tracking the legislative and consumer agenda on the elimination of lead from electronic products. We have also been assessing potential issues. The review of industry trend reveals the unique characteristics in selecting lead-free alternatives in each country. For instance, U.S. companies prefer the pure tin (matte tin) as component plating. Some Japanese companies selected Sn-Bi plating. There has also been some movement toward standardization of what is meant by 'lead-free.' In July 2001, Philips Semiconductor, Infineon Technologies, and STMicroelectronics proposed the standard for defining 'lead-free' components as 0.1 percent related to the individual material. In November 2001, JEDEC approved a definition for 'lead-free' solid-state components to contain no more than 0.2 percent by weight of elemental lead.
Electrical Characterization of Lead-Free Solder Coated Contact Interfaces: The contact resistance versus contact force characteristics of tin-silver-copper (SnAgCu) and tin-lead (SnPb) solder plated separable contacts were measured and compared. The effect on contact resistance of different aging conditions, including mixed flowing gas, steam, and dry heat aging was examined. Based on our contact resistance measurements, we find that the presence of silver and copper in the tested lead-free solder causes little adverse corrosive reaction to the aging conditions, compared with tin-lead solder processed using similar coating techniques (hot dipping). The use of the tin-silver-copper lead-free alloy as a contact finish is likely to be acceptable. However, high contact force is suggested for the application of tin-silver-copper lead-free solder coatings. Fretting corrosion may be increased due to new oxides.
Creep Corrosion on Plastic Encapsulated Microcircuits Package with Noble Metal Pre-plated Leadframe: Noble metal plating of leadframes was initially introduced as an improvement over traditional tin-lead (SnPb) solder, due in part to its corrosion resistance. However, noble metal pre-plated leadframes have some inherent surface damage. Noble metals provide an ideal surface for the migration of corrosion products since they do not oxidize in ambient surroundings. Under certain circumstances, corrosion products can creep up to the component molding surface and cause current leakage between isolated leads, particularly dangerous to fine pitch devices due to their tight lead spacing. This phenomenon is known as creep corrosion. CALCE EPSC is now working with Telcordia and TI on studies to assess creep corrosion.
For more information on the lead-free projects, contact Drs. A. Dasgupta, M. Pecht, B.T. Han, P. McCluskey, D. Barker or D. Das.
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Starting in the early 1990s and accelerating through the present-day, legislation and consumer demand has increased pressure on original equipment manufacturers to design and manufacture environmentally friendly products. This push toward 'green' electronics forces the industry to actively seek alternatives to current electronic packaging materials while still ensuring adequate performance and safety.
One particular safety concern is flammability of electronics, which can be mitigated by the appropriate selection of materials used to construct electronic products. To mitigate this risk, flame retardants are incorporated into plastic encapsulants and printed wiring board laminates. In the most common plastic encapsulants, flame retardancy is acquired through the addition of bromine-based aromatic compounds, which are highly valued for their effectiveness and low cost, especially for their ability to ensure compliance with the industry flammability standards.
In recent years bromide has been replaced with phosphorous due to increasing environmental, health and reliability concerns about bromine-based compounds. Just as with bromine, phosphorus-based flame retardants (PFR) can be characterized by their chemical structure and how they are incorporated into the epoxy molding compounds. PFRs are primarily divided into organic and inorganic compounds.
Organic phosphorus-based flame retardants currently used in electronic applications are primarily organophosphates. They can be mechanically blended into the resin or reacted directly into the polymer chain. One of the advantages of organic phosphorus is that its reaction products with ambient humidity tend to be non-corrosive phosphorus compounds. This is not always the case with inorganic phosphorus compounds.
The primary inorganic phosphorus compound is red phosphorus. Red phosphorus is normally too reactive to be used in microelectronic applications due to its tendency to form phosphine gas and oxygen-containing phosphoric acids in the presence of humidity. A dual layer coating was developed to inhibit these reactions. The inner layer is an inorganic compound, such as magnesium hydroxide or aluminium hydroxide, designed to retard the creation of phosphoric acid. The outer layer is resin-based and is designed to control the formation of phosphine gas.
These improvements in red phosphorus flame retardant systems led to their incorporation into plastic encapsulants for integrated circuits (ICs). Sumitomo initiated mass production of red phosphorus containing epoxy-molding compounds around 1996. Sumitomo selected phosphorus because of its superior properties, especially in comparison to other halide replacements. The Sumitomo formulations that contained red phosphorus include 7351UT, 7351UL and 7351UQ.
Due to the recent introduction of red phosphorus containing fire retardants and their primary use in components operating in benign environments, the long-term behavior of red phosphorus-containing molding compounds has not been well defined. Manufacturers and operators of high-reliability electronics in extreme environments should ensure that this material system has been properly qualified for their lifetime requirements. For more information, contact Dr. Michael Osterman at 301-405-8023.
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Conductive whiskers have been identified as causing multiple costly failures in electronic equipment, and are known to grow from tin, zinc and cadmium finished surfaces. The re-emergence of pure tin as a plating finish for electronic parts in response to the lead-free electronics movement has raised concerns over tin whisker related failures. In an effort to understand the issues related to tin whisker formation and to assess the current risk, researchers at CALCE EPSC in combination with engineers from Raytheon, Honeywell, Boeing, the US Navy and other government agencies have issued an initial alert to raise attention to this potential problem. The researchers and engineers are assembling information to assist companies. The tin whisker alert is primarily focused on producers of high reliability electronics that have long life requirements such as satellites, aircraft and military hardware.
Tin whiskers are growths of single crystals of tin, typically only a few microns in diameter with lengths from a few microns to over a millimeter. In one reported case, a 10 mm long tin whisker was found. Tin whiskers can cause failure by producing unintended electrical connections between adjacent conductors of differing potential, producing transient or permanent electrical shorts. The demonstrated ability of whiskers to bend due to electrostatic attraction increases the probability of causing a short. In addition, whiskers can break loose, causing mechanical damage in slip rings, optical components or MEMS. In low-pressure environments, it is possible for arcing to occur from a tin whisker to an adjacent conductor, causing significant damage. This problem has been demonstrated in terrestrial vacuum tests and is believed to have caused several failures of satellites.
Tin whisker formation is believed to occur in response to compressive stresses within the finish produced by the plating process, intermetallic formation and/or a mechanical load. Depending on the situation, apparently whiskers can form even years later. While recent advances in plating processes have apparently reduced the tendency of some pure tin finishes to grow whiskers, there is currently no industry-accepted test to qualify a finish as whisker-free or whisker- resistant. Further, the process controls on the plating operation necessary to assure whisker-free or whisker-resistant plating have not been adequately defined so that all consumers can properly monitor the process.
To address the concerns related to tin whisker formation, a working group of engineers has been holding regular phone conferences to collect information. Present activities include the generation of a part supplier spreadsheet to provide information on current and planned finishes and the development of a tin whisker mitigation guide.
For more information on the lead-free efforts being conducted at CALCE EPSC and the on-going work related to the tin whisker alert, please visit the CALCE Lead-Free Forum Web Page located at http://www.calce.umd.edu/lead-free/ or contact Dr. Michael Osterman at 301-405-8023, Dr. Abhijit Dasgupta at 301-405-5251, or Dr. Patrick McCluskey at 301-405-0279.
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As integrated circuits and packaging becomes more complex, they also become less accessible to conventional fault isolation techniques. The industry is moving toward finer pitch dimensions and many layers of metallization, often with several ground and power planes that complicate non-destructive analysis. As the distance between the power and ground planes continues to decrease, a new type of failure mechanism in printed wiring boards (PWBs) has emerged: vertical shorting between the power and ground planes. This failure is called vertical filament formation. New techniques like SQUID microscopy can provide the failure analyst with tools to isolate the defects.
Printed Wiring Boards. A PWB is the foundation for virtually all electronics in the world. It is the platform upon which electronic components are mounted. The PWB provides both the physical structure for mounting electronic components as well as the electrical interconnection between components.
A PWB consists of a non-conducting substrate (typically fiberglass with epoxy resin) upon which a conductive pattern or circuitry is formed. There are three types of PWBs: single-sided, double-sided and multilayer. Single-sided boards have a conductive pattern on one side only, double-sided boards have conductive patterns on both faces, and multilayer boards consist of alternating layers of conductor and insulating material bonded together.
Finding Failures. Once a defect in a PWB is detected via electrical testing, the location of the fault must be isolated in order to characterize the defect. Through the use of a SQUID (Superconducting Quantum Interference Device), current paths in integrated circuits and PWBs can be imaged via the magnetic fields they produce. These images can reveal the locations of shorts and other current anomalies at both the die and package levels.
Scanning SQUID Microscope. The Scanning SQUID Microscope is a sensitive near-field magnetic imaging system. A picture of the MAGMA-C10 SQUID Microscope is shown in Figure 1. This microscope can image buried current-carrying wires by measuring the magnetic fields produced by the currents, or it can be used to image fields produced by magnetic materials. By mapping the current in an integrated circuit or a package, short circuits can be localized. Designs can be verified by ensuring that charge is flowing where expected. The sensitivity of the SQUID is high enough to image currents as small as 600 nA at a 100 mm working distance with 30 ms averaging.
Example of Short Location Isolation. In one example, a twenty layer PWB had a short between the power and ground plane. Initial rough scanning gave an idea of the general location of the short via mapping highest current density while powering the device. After initially locating the area of highest current density in the board, the SQUID microscope was again employed; this time at a higher resolution. The resulting current density image is shown in Figure 2. After the location of the defect was determined using the SQUID, cross-sectioning enabled optical viewing of the defective area. An optical photo of the failure site after cross-sectioning and polishing is shown in Figure 3.
Conclusions. Cutting edge technologies use printed wiring boards where the spacing between the power and ground planes may be less than 2 mils. Electrical testing can verify that a problem exists between the power and ground planes, but these tests are virtually useless when it comes to determining their locations in the x-y plane, since the power and ground planes are copper sheets usually spanning the board's length and width. To meet these types of failure analysis needs, new techniques are required.
SQUID microscopy can be a very effective means of fault isolation in electronic assemblies. This technology is able to directly measure current in a non-contact, non-destructive way.
For more information, contact Dr. Keith Rogers at 301-405-5316.
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The interdependency of hardware and software leads to trade-offs in the optimum partitioning of functionality between hardware and software in the implementation of a system. While hardware and software have typically been described and designed using different formalisms, languages and tools; hardware/software co-design methodologies attempt to integrate the respective design techniques with the goal of utilizing a single design methodology in the system design process. Despite the advantages predicted from the utilization of co-design methodologies, co-design tools are not yet an integral part of most design processes and generally focus only on the prediction of system performance or co-verification of system functionality. New research at CALCE EPSC extends the conventional focus of hardware/software co-design through the development of a new methodology and a design tool called Ghost that evaluates system development, fabrication and testing costs concurrent with hardware/software partitioning in a co-design environment.
The new methodology utilizes a commercial co-design platform to analyze a virtual prototype of a mixed hardware/software system. A digital camera, considered a good representation of a mixed system, is modeled using functional and architectural block diagrams. System performance is simulated. Based on the determination of key metrics such as gate count and lines of software code, a software tool called Ghost developed at CALCE EPSC, evaluates software and hardware development, fabrication and testing costs. Using the co-design environment in conjunction with the Ghost tool (below) allows the concurrent evaluation of effects of hardware/software partitioning choices on cost and performance.
The detailed case study of the digital camera’s JPEG encoder chip reveals that production characteristics such as production quantity, level of reuse, and hardware/software partitioning have an effect on the optimal design under cost and performance standards. The influence of recurring and non-recurring costs is also demonstrated.
For further information on hardware/software co-design efforts at CALCE EPSC, please contact Dr. Peter Sandborn at 301-405-3167.
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1. CALCE Wins Air Force Contract
Two new MOCA (Mitigation of Obsolescence Cost Analysis) software tool research contracts have been awarded to CALCE EPSC.
Both contracts extend and verify the MOCA tool developed by the Physics-of-Failure Approach to Sustainable Electronic Systems (PASES) program.
One contract, through the CPOM program at Northrop Grumman, will demonstrate MOCA on an F-22 module and integrate MOCA with the POET design environment from
Titan Systems. The other contract is through an Air Force Small Business Innovative Research with Frontier Technology and will integrate MOCA with the ICE (Integrated
Cost Estimation) tool. The MOCA tool is available for downloading by CALCE members through the Design Refresh Planning-MOCA Software webbook on the CALCE website.
For more information, contact Dr. Peter Sandborn at 301-405-3167.
2. CALCE Wins Lockheed University Grant
Professor Peter Sandborn has received a Lockheed-Martin University Grant for research on pro-active design for part obsolescence mitigation.
The research focuses on developing a methodology for making optimal value-based decisions about how to refresh a system’s design using Bayesian Belief Networks (BBNs).
This methodology is embedded within the MOCA software application that determines the optimum design refresh (redesign) schedule for long field life
electronic systems based on forecasted electronic part obsolescence and a mix of obsolescence mitigation approaches ranging from lifetime buys to part substitution.
The specific solution being explored is a Monte Carlo/BBN hybrid in which candidate design refresh plans are determined through a Monte Carlo analysis of planned product
events and spare replenishment requirements. The BBN is used to make specific part or part group upgrade decisions at candidate design refresh points.
For more information, contact Dr. P. Sandborn at 301-405-3167.
3. New CALCE Book on Obsolescence
Life Cycle Forecasting, Mitigation Assessment, and Obsolescence Strategies by M. Pecht, P. Sandborn, R. Solomon,
D. Das and C. Wilkinson, CALCE EPSC Press, ISBN 0-9707174-1-5.
Electronic parts obsolescence is a serious problem causing millions to be expended on recovery actions and seriously compromising the long-term sustainability of systems. While technological advances continue to fuel product development, it is the engineering decisions about how and when to use a new part or technology and the trade-offs of associated risks and benefits that differentiate the winning from the losing products.
This book presents a methodology to forecast the years to obsolescence and the life cycle stages of electronic parts using part sales and technology trend data. It also presents the underlying reasons for part obsolescence and a wide variety of tactics and strategies that can be deployed by the part user to mitigate the effects.
For table of contents and purchasing information, go to here.
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