CALCE has completed development of rapid modeling software to assess
the durability of Pb-free package-to-board interconnects under life
cycle loading conditions. The Pb-free durability model is part of the
calcePWA software and is based on research conducted at the CALCE EPSC.
With the movement to Pb-free accelerating as the 2006 deadline
rapidly approaches, OEMs face a number of challenges. One challenge is
the package-to-board interconnect reliability due to stresses during
temperature cycling. While there is a general consensus that Pb-free
interconnects will be at least as durable as current SnPb
interconnects, tests have indicated that this may not always be the
case.
Over the past four years, CALCE has conducted investigations
to characterize the behavior of the leading Pb-free solder candidates.
In this effort, the constitutive and durability properties of selected
Pb-free solders have been determined. While there is still some
question as to which Pb-free solder compositions will be used, the
SnAgCu solder appears to be the leading candidate for reflow.
To address the interconnect durability issue, CALCE has
developed various modeling techniques to assess the life expectancy of
Pb-free solder interconnects. Simulation techniques range from detailed
finite element modeling of packages subjected to cyclic stress to rapid
life assessments contained within the calcePWA software. CALCE has
validated these modeling techniques against both internal and external
data.
The calcePWA software is capable of assessing life expectancy
of printed wiring assemblies under anticipated life cycle loads. The
simulation software includes capabilities to import and analyze designs
from Mentor, Cadence, and PADS. The software can be used to create a
simulation model of a printed wiring board assembly. The software
includes modules to conduct thermal and vibration response assessments,
as well as failure assessment modules. The Pb-free update allows the
software to be used to assess durability of SnAgCu solder interconnects
of leadless, ball grid array, PQFP, and other leaded packages subjected
to temperature cycling.
For further information regarding the CALCE software, please contact Dr. Michael Osterman.
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Dr. Das, a Six Sigma Black Belt, has developed customized Six Sigma
Green Belt and Black Belt training materials for Celestica, a leading
electronics manufacturing services provider. The training has improved
the Six Sigma program at Celestica by the enhanced cost-effectiveness.
For more information about the customized Six Sigma training materials,
contact Dr. Diganta Das.
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Electromagnetic interference (EMI) in high-speed digital and analog
circuits is considered one of the most critical challenges to the
electromagnetic reliability of modern-day electronic systems. These
challenges are exacerbated by the decrease in the threshold level in
digital logic, and by the increase in clock and bus speeds, which have
already exceeded the 1GHz mark. Electromagnetic interference is a
complex mechanism that takes place at different levels including the
chassis, board, component, and finally, the device level. Each one of
these represents a stage in the overall electromagnetic coupling
mechanism. Mitigation of electromagnetic noise follows certain
modalities and strategies that depend directly on physical topology and
material. In most previous works, the traditional approach to
mitigating EM noise is through hardening, variation of topology,
variation of material, or alternate electronic circuitry design
techniques, which can include the use of additional circuitry
components. While excellent shielding can always be achieved, however,
the consequent cost can be significant, especially in the sizable
sector of electronic systems that are very cost-sensitive. Therefore,
new noise mitigation paradigms are becoming more relevant and
necessary.
In recent months, the Electromagnetic Compatibility and Propagation Lab,
a CALCE member laboratory, introduced a novel concept to mitigate noise
in electronic circuit boards. This new concept employs high-impedance
surfaces (HIS), or electromagnetic band gap structures, to address
critical electromagnetic noise problems in high-speed circuits,
packages, boards, and cavities. HIS structures were originally proposed
in 1999 by a UCLA research team to enhance the propagation behavior of
printed antennas. The EMCPL team, lead by Prof. Omar M. Ramahi,
discovered a use for HIS that dramatically advances the limited scope
of antenna design. By inserting a simple HIS structure, shown in Fig.
1, within the parallel power planes used in printed circuit boards,
they found that a stop band effect can be created at the location of
the major clock harmonics that give rise to increased radiation. These
novel ideas and designs have been rigorously tested using numerical
simulations and prototypes have been simulated, designed and tested.
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With flip-chip technology, the top surface of the chip is available
for enhanced thermal management solutions. In the interposer or cap
configuration, an interposer is present between the chip and the heat
sink, which allows use of non-adhesive interstitial materials with
higher thermal conductivity, such as thermal grease, thermal gel,
elastomeric gasket, phase change material and so on. This configuration
has become increasingly important as power densities increase rapidly.
However, the inherently great warpage of FC-PBGA packages poses a new
technical challenge in the high performance thermal solution, i.e.,
non-uniform thermal conductance at the chip/interposer interface.
When the chip is powered, the non-uniform CTE distribution
produces thermally induced warpage in the chip and substrate.
Consequently, the gap between the chip and the interposer changes
repeatedly under a device operation condition (power cycling), as
illustrated in Fig. 2.
If non-solid interstitial materials are used, the gap change
reduces the volume of the material. The material is gradually squeezed
out during the repeated power cycling, which eventually causes
significant degradation of thermal performance; this phenomenon is
known as “pump-out.?
It is important to note that the volume change during power
cycling is directly proportional to a change in the total warpage of
the package, since the interposer is mechanically connected to the
substrate. For the fringe patterns shown in Fig. 2 (obtained by far
infrared Fizeau interferometry), the warpage change in the package can
be as large as 50 mm. This would reduce the original volume of thermal
grease or gel significantly and should be considered in the design of a
thermal solution for performance as well as reliability.
Fig. 2 Warpage contours of FC-PBGA package
documented at (a) 150°C, (b) 100°C and (c) room temperature, where the
contour interval is 5.3 mm per fringe order. A 3-D warpage map at room
temperature obtained by digital image processing is shown in (d).
For more information, contact Dr. Bongtae Han.
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Due to severe, harsh environments in the aerospace industry, the
long-term reliability of commercially available plastic ball grid array
(PBGA) packages faces challenges. In an effort to understand the
implications of using commercially readily available packages for the
aerospace industry a large design of experiment (DOE) was completed.
Experimental results and failure analysis were analyzed by CALCE EPSC.
Virtual qualification was also performed to evaluate solder-joint
reliability under thermal cycling and vibration loadings.
Design of Experiments (DOE)
As Table 1 summarizes, the DOE variables included conformal
coating methods (spray or dip), PCB pad types (solder-mask defined
(SMD) or non-solder mask defined (NSMD)), and underfilling or
non-underfilling the ball grid array with epoxy. A matrix for the tests
can be found in Table 2. Each cell of the DOE was comprised of all
groups from Table 1. For tests 1-4, PCBs experienced air-to-air
temperature cycling (AATC) and vibration concurrently. Tests 5 and 6
only had vibration testing. AATC alone occurred during tests 7 and 8.
Experimental Results and Failure Analysis
Thermal cycling tests revealed that high-temperature cycling
(-50/150°C) caused more packages to fail than low temperature cycling
(-40/125°C) did. Vibration loading did not fail as many packages as
temperature cycling. Multiple stresses, i.e., thermal cycling and
vibration loadings concurrently, accelerated the damage on packages
with more and earlier failures than either thermal cycling alone or
vibration alone.
Test results also verified that underfilled packages had better
reliability than non-underfilled packages under all stress conditions.
On the other hand, different board pad types (SMD or NSMD) and
conformal coating methods (spray or dip coating) did not affect the
life of packages as much as underfill did.
Non-destructive and destructive failure analyses were performed
on test samples. Electrical probe tests showed electrical opens or high
electrical resistance with failed packages. Through analysis of
cross-sections, the failure mode of non-underfilled packages was
identified as fatigue cracks that initiated at solder-joint corners and
propagated through the solder layer near the component or board side,
or both sides, as shown in Fig. 3.
Virtual Qualification
Virtual qualification has been accepted as a cost-effective tool
for electronic packaging designers. The methodology of virtual
qualification is to assess and improve the durability of electronic
equipment through the use of validated failure models. For this study,
the life of non-underfilled PBGA under thermal cycling was predicted
using a Coffin-Manson fatigue damage model and first order interconnect
stress model, which were integrated in existing software, calcePWA. The
simulation results were close to the experimental results. For
instance, the prediction to measured ratio was 1.07 and 1.14 under
?0/125°C and ?0/150°C loadings, respectively.
Simulation of the test board under the vibration test
conditions indicated a distribution of time to failures based on the
position of the components. The test boards were rectangular and
contained 15 components in a 5 by 3 row pattern. Based on the support,
the board had a relatively high natural frequency. Components located
in high curvature locations were estimated to have a considerably lower
life expectancy than components located in low curvature locations. The
simulation results were validated through the vibration only tests
where the test boards were subjected to over 2000 hours of vibration.
Fig. 3 A Cross-section Image from a Non-underfilled Package after Thermal Cycling Tests
For more information, contact Dr. Michael Osterman.
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Increasingly electronic systems are being considered for
applications that require operation at temperatures and forces that
exceed traditional levels. This includes the low temperatures
encountered in deep space missions, the high temperatures encountered
in the engine compartment of automobiles and aircraft, the high-g
environments encountered in military hardware, and the combined extreme
temperature and high g-force environments encountered in deep well
drilling. The electronic devices, sensors, and packaging for these
environments have significantly different requirements than those for
standard commercial applications. These requirements are addressed both
by the development of new processes and technologies, and by the
uprating of existing technology. As a center of excellence for extreme
environment electronics research, the CALCE EPSC is currently
conducting a number of major efforts.
High-temperature electronics research at the CALCE Electronic Products and Systems Center is focused on the following three fronts:
- development of new technology for very high temperature (T >300°C) applications
- process integration and reliability assessment of
technology for mid-high temperature applications (200°C < T <
300°C)
- extension of the use of commercial technology into the most
modest high temperature applications (125°C < T < 200°C)
An example of our work in the first area is the development and
reliability assessment of packaging for a 500°C SiC MEMS pressure
sensor and associated SiC electronics for supersonic engine control. In
this work, we are evaluating the stresses generated in pure silver and
gold die-attach materials as a function of temperature cycling and
power cycling at high temperatures, and their effect on the calibration
of the pressure sensor. We are also investigating the fatigue of
wirebond interconnections under these same temperature- and
power-cycling conditions.
In the second area, we are conducting a full virtual
qualification and reliability assessment of a series of hybrid
multi-chip modules for an oil well drilling tool. This work involves
using a set of ceramic hybrid failure mechanism models that have been
developed over the last several years for substrate fracture, die
attach fatigue, and wedge wire-bond fatigue under power and temperature
cycling. The oil well environment also requires assessment of
reliability under high shock and vibration loadings.
In the third area, we have developed a reliability assessment
model for the formation of gold-aluminum intermetallics in commercial
devices at temperatures above 125°C as a function of the bromine flame
retardant concentration in the plastic-encapsulation. In addition, we
have developed a test procedure for determining the susceptibility of
plastic encapsulated microelectronics to bromine-induced early
intermetallic failure. Finally, we have assessed the susceptibility to
intermetallic failure of devices made with a series of halogen-free
molding compounds and shown improved high-temperature storage and
operating life for devices made with these new, environmentally
friendly encapsulants.
For further information on these efforts, please contact Dr. Patrick McCluskey.
Low-temperature electronics research at the CALCE Electronics Products and System Center is focused on the following two fronts:
- performance and reliability aspects of low temperature electronics between 0°C to -70°C.
- physics-of-failure (PoF) analysis of chip-on-board (COB)
packaging technology for low temperature (-120°C) and 205°C-range
temperature cycling applications.
The first focus area stems from the need for OEMs in avionics,
networking and communications to develop cost-effective systems
deploying commercial-off-the-shelf components without resorting to
expensive and cumbersome methods, like selectively attaching heated
plates on the PCB assemblies. Even though a significant knowledge base
exists on the low-temperature physics of electronic devices, it is not
specific to the products used in an application. Moreover, for various
reasons, including availability and cost, the OEMs are confronted with
the problem of using parts rated for a commercial range (0°C to 70°C).
Thus, in this research focus we intend to expand the knowledge base on
the performance of these parts at low temperatures through theoretical
analysis and experimental characterization. The parts being
investigated encompass many technologies including CMOS logic, CMOS
memories, RF devices (amplifiers, oscillators, filters, couplers, and
modulators), optoelectronic modules, analog devices, and passives. We
believe this knowledge base will help many consortium members with
applications deploying commercial-range parts at low temperatures.
The second focus is on PoF analysis of COB technology for low
temperature and large cyclic temperature-range space mission
applications. In this effort, we intend to identify key failure
mechanisms, characterize packaging materials and interfaces at low
temperatures, and develop and validate models to determine the stress
on wire bond interconnects and chip.
For further information on these efforts, please contact
Dr. Sanka Ganesan.
High-g electronics. CALCE is working closely with ARL to
identify the most dominant failure sites and failure mechanisms in gun
launched smart munitions containing electronic components and
assemblies. Next generation artillery rounds need to survive setback
loads of 15,000 to 60,000 peak G levels. An intermediate objective of
the project is to provide electronic assembly and component selection
design guidelines for high-g applications. The final objective is to
validate design models and methodologies that can be used for the rapid
reliability assessment and virtual qualification of electronic
assemblies in smart artillery projectiles. The project may initially
seem beyond the typical environment seen by most electronics, but the
design models and methodologies developed in this effort will yield
improvements that can be applied to much tamer and more typical shock
and vibration loads seen by a wide cross-section of electronics.
For further information on these efforts, please contact
Dr. Donald Barker.
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