| Objectives | Background | Approach |
In 1995-1997, CALCE developed a five-step PoF approach for maximizing test-time compression by simultaneously applying different environmental loads. This approach was demonstrated on electronic circuit card assemblies (CCAs) using combined vibration and thermal cycling. PoF models such as Incremental Damage Superposition Approach (IDSA) were developed to capture the interactions between different stresses (e.g. vibration and thermal stresses) and to develop accurate acceleration factors. In the two subsequent years, 1998-1999, a similar effort was initiated for screening of electronic assemblies . Detailed guidelines for designing and implementing screening programs were developed. CALCE created a comprehensive web-based facility to interactively help users implement this PoF approach through the use of detailed flowcharts, worksheets, models, databases and on-line analysis tools.
Last year, a project was undertaken to demonstrate the use of these flowcharts through case studies. An accelerated qualification was conducted on a high volume automotive electronic unit and a low volume military unit. This year (as a continuation of C00-52), the implementation of screening guidelines is being demonstrated on two fully functional electronic assemblies (low-volume avionics system). The virtual qualification and the accelerated testing on sponsor's selected products have been already performed (C00-52 project). Techniques for tailoring stress profiles to specific products are being demonstrated on the sponsor's product. Application of stress optimization techniques are being explored.
As a second objective, a comprehensive study is being condcuted to clarify the issues that govern test time compression in acceleration thermal cycling of electronic CCAs, which include the effect of ramp rates and dwell times. Prior experience provided conflicting indications about optimal combinations of ramp rate and dwell time. The impact of this study will be to provide guidelines for optimizing test time compression and for increasing effectiveness of temperature cycling tests. Specifically, we will seek to demonstrate the effect of different temperature histories on thermal cycling damage in electronic assemblies and propose guidelines for maximum test-time compression in accelerated temperature cycling tests.
· Objective 1: the implementation of screening flowcharts will be demonstrated on two circuit card assemblies. This flowchart is based on a PoF approach. As a first step, a virtual qualification is conducted (simulation of the boards undergoing their life cycle loads), followed by the definition of the Acceleration Life Test (ALT) profile based on the results of a limit test of the product. This ALT will be conducted at the sponsor's site and the virtual test simulation will be conducted at CALCE using CalcePWA software. An acceleration factor will finally be extracted to assess the design life and life margins and a screening profile will be recommended based on life margin.
· Objective 2: Various techniques for achieving maximum test time compression in accelerated thermal cycling will be explored through a Design of Experiments (DoE). Specifically, accelerated thermal cycling tests will be conducted at various pre-determined levels of dwell times and ramp rates. The test results and PoF analysis will be used to develop guidelines for optimizing test time compression. Technology transfer to member industries will be in the form of on-line documentation, guidelines and workshops.