Project Number: C01-36

Effect of Lead Free Solder Reflow Profiles on the Component Integrity

Dr. Pecht pecht@calce.umd.edu

Objectives Background Approach

Objectives


Background

Common lead free solder materials proposed by industry groups and adopted by companies have a higher reflow peak temperature than that of traditional tin-lead (SnPb) solder. Electronic components will be exposed to higher temperature for some period during solder reflow process. Table 1 shows the comparison between eutectic 63Sn37Pb reflow soldering parameters and Sn0.7Cu3.6Ag lead-free reflow soldering parameters. The maximum temperature is about 35oC higher for the lead free solder material. This higher temperature may pose serious impacts on electronic component integrity, such as effects of thermal stress mismatch and hygro-thermal-stress mismatch. The reflow process thus may introduce defects to parts.

Table 1: Comparison of eutectic SnPb soldering parameters and SnCuAg lead-free soldering parameters (Source: Edwin Bradley and J. Bath, "Lead free project focuses on electronics assemblies," Advanced Packaging, February 2000, pp. 34-42.)

Condition Existing J Standard 020 A Lead-free Soldering
Average ramp up rate to melting point 3oC/sec (max) 2.5 - 3oC/sec (max)
Pre-heat dwell time and temperature 60-120 sec (max) at 125oC (+/-0 25oC) 60-120 sec (max) at 125oC (+/-0 25oC)
Time above melting point 60-150 sec 80 sec
Time within 5oC of actual peak 10-20 sec 10-20 sec
Peak temperature range 220oC (+5/-0 C) 255oC (+5/-0 C)
Ramp down rate 6oC/sec (max) 6oC/sec (max)
Time from 25oC to peak temperature 4 min- 6 min 6 min (max)


Approach

One of the most urgent and important issues for lead-free solder implementation is the impact to electronic components that were already built for SnPb soldering process. Test vehicles will go through preconditioning test with simulated lead-free reflow soldering process. An experimental setup developed at CALCE that simulates the reflow profile and measures the mechanical deformation during the simulation will be used for this test. Furthermore, temperature cycling (TC) and highly accelerated stress test (HAST) will be carried out to further investigate the impacts of lead free solder reflow on electronic components integrity. Failure analysis techniques will be used throughout the evaluation to detect failure sites and failure mechanisms. The test vehicles will be selected in consultation with the member companies. The steps that will be followed are:

  1. Select lead-free reflow soldering profiles and define the important parameters in reflow soldering.
  2. Soak components based on JEDEC moisture sensitivity specifications.
  3. Simulate lead-free reflow soldering processes and measuring/monitoring device temperature and/or component displacement, electrical signals in real time.
  4. Subject test components to a variety of test conditions: moisture, thermal soak, thermal cycling with in situ monitoring
  5. Failure analysis of tested components through electrical testing, C-SAM, destructive analysis and SEM
  6. Report failure sites and mechanisms, and provide manufacturing guidelines

The work will also include industrial information gathering regarding the modifications made by major packaging houses to their components to account for lead free soldering. Practices in Japanese electronics manufacturers and their part suppliers who have already migrated to the lead free solders will be reported.

Copyright © 2001 CALCE and the University of Maryland. All rights reserved.