Project Number: C93-15

Temperature Dependence of Microelectronic Device Failures

Point of Contact: Dr. Michael Pecht email: Pecht@calce.umd.edu Phone: (301) 405-5323 Fax: (301) 314-9269

Objectives

Background

Work Accomplised

Objectives

Quantify the role of steady-state temperature, temperature-cycle magnitude, temperature gradient, and time-dependent temperature change in device failure mechanisms and electrical performance parameters for BJT and MOSFET, in the equipment operating range of -55 to 125øC.
Derive physics-of-failure based guidelines for thermal derating of microelectronic devices current guidelines involve lowering the junction temperature. Use the identified models for various failure processes to evaluate the sensitivity of device life to variations in manufacturing defects, device architecture, and non- temperature stresses versus temperature stresses.

Background

Thermal derating criteria are often based on the common belief that reliable electronics can be achieved by lowering temperature. Elevated temperature has in the past been considered a dominant stress that lowers reliability, so every effort has been made to lower operating temperature until the desired reliability is achieved [Dantowitz 1971, Manno 1983, Westinghouse 1989, DELCO 1988, Devanay 1989, Bloomer 1989, Semiconductor Reliability News 1990, Witzman 1990, BT 1984, CNET 1983, MIL-HDBK-217, NTT 1985, RPP 1988]. The problem arises when there is no way to evaluate the temperature sensitivity of the device design. Currently, when there is no scientific tool to answer such questions as, Is there a need for lowering temperature? If so what is the value of the lower temperature as a function of device architecture? How does the maximum operating temperature vary with design? What design modifications are necessary to vary the maximum allowable operating temperature for a desired mission life? How do manufacturing defect magnitudes affect the time to failure? Is it possible to change any other form of stress than temperature to achieve the desired mission life and still escape the penalty of the added cost and weight of a cooling system? This paper attempts to address these questions.

Existing thermal derating procedures give the design team a false sense of security about achieving increased reliability at lower temperatures. Lower temperatures may not necessarily increase reliability, since some of the failure mechanisms are inversely dependent on temperature; for example, device technologies with hot electrons as the dominant mechanism may have lower reliability at lower temperatures. Even for microelectronic technologies in which temperature is a dominant failure accelerator, steady-state temperature thresholds, affecting device sensitivity to various forms of temperature stress, are a function of device architecture, materials, manufacturing defects, and other non- temperature-related operational stresses. Assigning a generic value of lower temperature to a technology, based on the assumption that all devices operating at that lower value of temperature will be reliable, is thus arbitrary.

Current thermal derating guidelines do not account for the dominant failure mechanisms or their temperature dependencies [Brummet 1982, Eskin 1984, Naval Air Systems Command AS- 4613 1976, Westinghouse 1986]. Temperature- cycle effects that have not been accounted for in device derating criteria are failure accelerators at mating interfaces. The maximum number of temperature cycles that the device can endure is a function of fatigue failure mechanisms, such as wire-interconnect fatigue, die fracture, or die and substrate attach fatigue. These mechanisms may or may not be dominant in the device architecture, depending on the stresses generated at the mating interfaces, which are a function of interface geometry, and on material characteristics, including CTE mismatches.

Current device derating guidelines do not account for temperature gradient effects on reliability. Typically, localized temperature gradients exist in the chip metallization, chip, substrate, and package case, due to sudden variations in conductivity produced by defects in the form of voids or cracks. The locations of maximum temperature gradients in chip metallization are sites for mass transfer mechanisms, including electromigration. Electromigration is also accelerated by temperature and current density. Therefore, device reliability - for mechanisms with a dominant dependence on more than one operating stress (temperature and non- temperature), complicated by dependence on magnitudes of manufacturing defects - needs to be maximized by more than just lowering temperature, as existing derating criteria do.

Interaction of various temperature and non- temperature stresses that modify the dominant dependence of failure mechanisms on one or more of the stresses is not accounted for in current thermal derating methodology. Temperature transients generated by the duty cycle (ON/(ON+OFF)) modify the dependence of the metallization corrosion on steady-state temperature. At low duty-cycle values, metallization corrosion has a dominant dependence on steady-state temperature. However, at higher values ( ÷ in neighborhood of 1.0), metallization corrosion has a dominant dependence on duty-cycle and a mild dependence on steady-state temperature.

Work Accomplished

Identification of existing physics-of-failure models quantifying the dependence of failure mechanisms on steady-state temperature, temperature cycle magnitude, temperature gradient, and time-dependent temperature change.

Determination of an upper temperature limit, based on actual negative effects of steady-state temperature, temperature cycle, temperature gradient, and time- dependent temperature change that must be avoided for performance parameters and failure mechanisms having temperature dependencies.

Derating curves for constant device life are derived for mechanisms with complex dependencies on stresses and defects. The cumulative effect of competing failure processes on device life is used to determine the values of operating temperature and non-temperature related stresses.

A set of derating guidelines for temperature-tolerant design for performance and reliability has been derived based on the results of these investigations.