| Created: 5/21/95 |
Updated: 4/18/97 |
Finite Element Modeling of Advanced Interconnections
Objectives
Develop detailed finite element analysis
(FEA) models that allow computation of
thermal, thermo-mechanical, and mechanical
responses for advanced interconnect
technology (AIT) packages.
Background
AIT packages are multichip modules (MCMs)
that utilize advanced packaging technology for
interconnections between chips. For new
technologies, it is important to understand
potential reliability problems and failure
mechanisms in order to develop suitable
technology characterization and qualification
procedures. This modeling effort forms part
of a joint NASA-Army-Navy-Air Force
Reliability Technology (RELTECH) program
to develop a detailed understanding of the
reliability of AIT structures in space and
military environments. New packaging
technologies will be analyzed, such as
overlaid high-density interconnects (HDI),
which places active chips within wells formed
on the substrate and then overlays dielectric
layers containing current traces for
interconnection. nChip's MCMs and such
other technologies as three-dimensional die
stacks are also being examined as part of the
program.
Approach
- Develop global and local three-dimensional
FEA modeling approach for analyzing AIT
structures. The global models provide
analysis at the package level, while the
local models provide refined analyses of
specific vulnerable substructures.
- Develop a procedure for globally modeling
dimensions for such structures as the
substrate, the wells within the substrate,
and the chips.
- Establish methods for local modeling of the
geometry of structures such as vias, bond
pads, metallization lines and various
material interfaces.
- Validate the approach by modeling and
analyzing AIT structures.
Work Accomplished
- Global and local finite element models
have been developed for HDI technology,
and thermal and mechanical FEAs have
been performed for an HDI test structure
and an actual production structure.
- Software tools have been developed for
automating model building, material
database entry, FEA, and the display of
results.
- JPL has interfaced the AIT module with the
NASTRAN FEA code.
- Models and automation software have been
developed for n-Chip's MCM and three-
dimensional die-stacks.
- General purpose finite element modeling
automation tools for electronics packaging
have been developed and integrated into
P3/PATRAN.
