EXECUTIVE SUMMARY:

HAST tests were conducted on SOT-23 (TO-236AB) packaged npn transistors from Motorola and Philips. The samples were soldered onto polyimide printed circuit boards, subjected to 30 temperature cycles from -55¡ãC to 85¡ãC, and then exposed to an environment of 130¡ãC, 85%RH under reverse bias for 200 hours. Measurements of the specified DC device parameters were taken before exposure and after every 50 hours of exposure. Decreased breakdown voltage would have indicated field distortion, while increased saturation voltage or increased I_EBO leakage current would have indicated corrosion damage. After 200 hours of exposure, all the devices passed the manufacturer's specifications for breakdown voltage, saturation voltage, or I_EBO leakage current. Using currently accepted acceleration factors, these results indicate that these devices will survive for more than 20 years in a 30¡ãC, 60% RH application environment.

INTRODUCTION:

Plastic encapsulated microcircuits (PEMs) have come into widespread commercial use because of their low per part cost, small size, light weight, and, in many cases, significant performance advantages. As a result of these favorable qualities, more than 97% of all current ICs are packaged in plastic [1]. This widespread availability of PEMs comes at a time when the availability of alternative ceramic packaged microcircuits is decreasing. This is a result of the closing of the military divisions of major semiconductor manufacturers, such as AMD and Motorola, in response to the statement by the office of the Secretary of Defense encouraging the use of parts produced using best commercial practices. For these reasons, many electronic equipment manufacturers are now considering using PEMs in severe environments.

However, there is concern over the use of PEMs in harsh environments because of their susceptibility to moisture-related failure mechanisms, including corrosion of metallization traces and bond pads [1]. This is a result of the inherent permeability of plastic materials to moisture and the residual ionic contamination present in plastic molding compounds. For this reason, plastic packaged ICs are often qualified using tests which accelerate failure due to moisture related failure mechanisms. The first test developed for this purpose was the temperature-humidity-bias (THB) test which was commonly run at 85¡ã C, 85% RH for 1000 hours. Over time, reduced extractable ionic contamination in the molding compounds, decreased moisture permeability, and improved die passivation, increased the times needed to provide a statistically significant number of failures to levels which were unacceptably long (>5000 hours). As a result, the highly accelerated temperature-humidity stress (HAST) test with its greater acceleration factor was substituted.

In this study, HAST testing at 130¡ã C, 85% RH was conducted for 200 hours to determine the susceptibility of discrete, plastic packaged, small signal, npn transistors to moisture-related degradation and failure during their operating lifetime. Fourteen npn transistors from each of two manufacturers were tested. These transistors were epitaxial discrete npn devices, as shown in figure 1, with an n+ emitter diffused into the epitaxial p base. Connection to both the emitter and base contacts is made by wirebonding to bondpads on the top surface of the die. Backside contact to the collector is made via the die paddle. There are two primary failure modes for this type of transistor when exposed to biased temperature-humidity stress. The first, which dominates at low bias conditions, is a perturbation of the electric field in the device as a result of the collection of water molecules in the active area on the surface of the die. This leads to a degradation in the breakdown voltage of the device. The second failure mode, which dominates at high bias conditions, is cathodic corrosion of the aluminum bond pads as a result of current flowing through the ionically conducting moisture layer above the device. This is evidenced as an increase in the collector-emitter saturation voltage and as an increased I_EBO leakage current. Failure in this study was therefore defined as operation outside of the manufacturer's performance specifications for breakdown voltage, I_EBO leakage current, and saturation voltage [2].

PROCEDURE:

Two sets of npn transistors were examined in this study. The first set contained 14 MMBT2222ALT1 transistors from Motorola and the other set contained 14 PMBT2222 transistors from Philips. The following procedure was used, with details provided below.

1) Bake devices at 125¡ã C for 24 hours to remove moisture.
2) Assemble devices onto HAST boards using vapor phase reflow as per MIL-STD-2000A.
3) Precondition assembled boards by temperature cycling (MIL-STD-883D, Method 1010.7.A.)
4) Perform initial electrical test of devices.
5) Clean boards in a dilute non-ionic surfactant, rinse with DI water, and dry at 125¡ã C for 1 hour.
6) Place boards in HAST chamber, fill chamber with DI water and program test chamber.
7) Expose boards to 130¡ã C, 85% RH for 200 hours, with electrical test every 50 hours.
8) Perform final electrical test.

Bake and Assembly 

Devices were baked for 24 hours at 125¡ã C before being assembled onto specially constructed printed circuit boards produced by HAST Solutions, Inc. of Santa Cruz, CA. These boards were 4.55" x 8.35" double sided polyimide-copper laminate boards (type 3003) with the emitter, base, and collector lines of each device routed to a gold plated finger on the edge connector, as shown in figure 2. Because of the small number of leads per device and the fact that the small size of the devices allowed them to be located near the edge connector, it was determined that an etched board would be acceptable for this study. Unetched socketed boards are often used for larger devices, where the greater size and number of leads requires a more sophisticated routing on etched boards that can lead to failure of the board through solder migration and shorting of the leads, before failure of the devices. Conformal coating of the board was also deemed unnecesary.

Devices were assembled on the boards by vapor phase reflow of eutectic SnPb solder paste. Board assembly was performed at Litton Industries, Inc., College Park, MD as per MIL-STD-2000A. Each set of 14 transistors was assembled onto a separate board. Assembling the devices onto the boards served two functions. First, it facilitated biasing the devices and measuring the electrical parameters during the test. Second, it exposed the devices to thermo-mechanical stresses representative of those that would be experienced during assembly into actual systems. The vapor phase reflow followed the profile of figure 3 with a maximum temperature of 219¡ã C and was performed with a Centech reflow unit. Following reflow the boards were cleaned in Marsolve 404 - (1,1,1) trichloroethane and n-propyl alcohol.

Preconditioning  

In order to include the effects of temperature cycling as well as temperature-humidity exposure, the assembled boards were subjected to 30 temperature cycles of -55¡ã C to 85¡ã C as per MIL-STD-883D Method 1010.7 test condition A, before being exposed to HAST. (see Appendix A) Thermocouples were placed on the boards to ensure that the extreme temperatures were reached and that the boards stabilized at temperature within the required 15 minute limit. The test was conducted over three days between November 10, 1995 and November 21, 1995 as shown on the traveler. Ten cycles were performed each day as per the specification.

Initial Electrical Test 

Initial electrical testing was performed using a Tektronix 5CT1N curve tracer. Tests were conducted on each device to measure the DC on-state and off-state characteristics specified on the manufacturer's datasheet. On-state characteristics included the collector-emitter saturation voltage. Off-state characteristics included the breakdown voltages (V_CEO, V_CBO, V_EBO), and the I_EBO leakage current. The saturation voltage, leakage current, and breakdown voltage parameters were of particular importance because they can be used to identify failure by the two most common moisture-related failure mechanisms. ESD precautions were observed, including the use of grounded wriststraps, an anti-static mat, and anti-static gloves whenever the boards were removed, tested, and reinserted in the chamber.

Pre-test Cleaning 

Following initial electrical test, the boards were cleaned in a dilute non-ionic surfactant, followed by copious rinsing in deionized water. The HAST apparatus was also cleaned by washing the inner chamber, the outer chamber, the fan, and the card cage with 10% IPA in deionized water, followed by copious rinsing with deionized water as per the specification in Appendix B. The chamber was reassembled and allowed to air dry overnight; the boards were dried for one hour at
125¡ãC.

Test Set-Up 

Assembled boards were then placed into a stainless steel (type 304) card cage. The cage provided a 1.3" center to center distance between boards for adequate flow of moist air across both surfaces of each board. The edge connectors of the boards were placed in 44-pin Ryton R4-04 gold-plated sockets which were routed such that all the emitters were commoned together into a single line, as were all the bases and all the collectors. Each of the three teflon coated leadlines was then fed out of the chamber through a teflon insulated terminal block. For the test, the devices were reverse biased with the emitter positive and the base and collector grounded. This provided a driving force for corrosion between the emitter and base traces, but did not allow any current to pass, thereby eliminating any power dissipation which might heat the die and stop the condensation of moisture necessary for corrosion and field distortion effects. The chamber provided microprocessor control of the ramp up, hold, and ramp down portions of the profile.

Exposure and Test

• Standby at 30¡ã C, 85% RH
• Ramp up to 130¡ã C, 85% RH in 90 minutes
• Turn on the voltage bias to the emitter
• Hold at 130¡ã C, 85% RH for 50 hours
• Turn off the voltage bias to the emitter
• Ramp down to 30¡ã C, 60% RH in 120 minutes.
• Hold at 30¡ã C, 60% RH until door is opened.

Room temperature DC parametric testing was conducted after each 50 hours as shown on the traveler. In each case the electrical test was performed within 48 hours of the end of the 130¡ã C, 85% RH exposure, but never sooner than 2 hours after the boards had been removed from the chamber. In all cases, the boards were returned to the chamber within 96 hours of the start of the ramp down.

The acceleration factors for the 130¡ã C, 85% RH test condition relative to the 85¡ã C, 85% RH THB test and to standard use conditions (30¡ã C, 60% RH) are given in table 1. These factors are based on the Peck model [3]. A trailer is included in Appendix D which lists the times and dates at which each segment of the testing was completed.

RESULTS:

The electrical data collected on each device before testing and after each 50 hours of exposure is provided in Appendix E together with the manufacturer's specified limits for each characteristic. The Motorola devices performed within specification for the entire 200 hour exposure. The saturation voltage remained at 0.2 volts after a slight decrease to 0.1 volts after 50 hours exposure. This is below the 0.3 volt maximum allowed and indicates that there is not a concern with corrosion in these devices. The changes in V_CEO from an average of 51.7 ± 1.9 V at initial test to an average of 50.8 ± 1.1 V after 200 hours exposure, and in V_CBO from 137.4 ± 1.4 V to 139.1 ± 1.0 V were statistically insignificant. V_EBO increased slightly from 7 V to 7.2 V. In each case, the voltages were well above the specified limits. This indicates that field distortion is also not a concern. Similarly, in no case did the leakage current approach the 10 nA limit set by the manufacturer.

The Phillips transistors stayed within specification for the entire 200 hours of HAST exposure, as well. The collector-emitter saturation voltage remained at 0.2 volts, and I_EBO stayed below the 10 nA limit throughout the exposure, indicating there was not a concern with corrosion in these devices. The change in V_CEO from an average of 55 ± 1.3 V at initial test to an average of 56.9 ± 1.9 V after 200 hours exposure was statistically insignificant, while the change in V_CBO from 86 V to 88 V, after dropping to 84 V in the first 50 hours, was not of practical significance as all three voltages were greater than the specified limit of 75 V. V_EBO stayed at 7.2 V throughout the test. These breakdown voltages indicate that field distortion is not a concern with the Philips transistors.

All the devices from both manufacturers are considered to have passed the test, since the saturation voltage, breakdown voltage, and I_EBO leakage current remained within the specified ranges. Given the established acceleration factors, this means that the devices can be expected to survive for more than 20 years in a typical application environment of 30¡ã C and 60% RH.
 

REFERENCES:

1) M. Pecht, L. Nguyen, and E. Hakim, Plastic Encapsulated Microelectronics: Materials, Processes, Quality, Reliability, and Applications, John Wiley and Sons, New York, 1995.

2) G. W. Neudeck, The Bipolar Junction Transistor, 2nd ed., Addison-Wesley Publishing Co., New York, 1989.

3) O. Hallberg and D. S. Peck, Recent Humidity Accelerations, A Base for Testing Standards, John Wiley and Sons, New York, 1991. pp. 169-179.