[Introduction] | [CALCE Role] | [Progress]
The objective of this program is to lay the ground work for the future implemenation of a Transmit Receive (TR) module on a single chip. In order to fabricate a TR module on a chip, compatible processes for fabricating high-speed transistors, MMIC, and MEMS must be developed and applied to a single wafer.
CALCE-EPSC is a subcontractor of the NASA Jet Propulsion Laboratory (JPL) on this program. CALCE will evaluate the manufacturing processes associated with fabricating advanced high-frequency modules composed of a combination of micromachined (MEMs) and electronic solid state components (Si/Ge HBTs). Evaluation of the manufacturing processes includes identification of the process steps, evaluating compatibility of the necessary processing, cost analysis, and yield analysis.
Phase 1 - Baseline Process Modeling and Process Compatibility Evaluation
Task 1.1 - Process Identification
Task 1.2 - Process Compatibility Evaluation
Task 1.3 - Process Model (Cost and Yield Analysis)
Phase 2 - Extensions to Baseline Models and Industry Evaluation of Processes
Task 2.1 - Test and Rework
Task 2.2 - Optical Interfaces
Task 2.3 - Industrial Evaluation
Process models for RF MEMS structures <CALCE MEMBERS ONLY>
Process models for Si/Ge HBTs <CALCE MEMBERS ONLY>
For further information on this program, contact Dr. Peter Sandborn, (301) 405-3167, sandborn@calce.umd.edu.